-
Notifications
You must be signed in to change notification settings - Fork 15.2k
[RISCV] Check the types are the same for folding (sub 0, (setcc x, 0, setlt)) to (sra x, xlen - 1) #158179
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Conversation
… setlt)) to (sra x, xlen - 1) We should check the type of x is the same as `sub` operation. Otherwise the shift amount xlen -1 will exceed the bit size of x. Fixes llvm#158121.
@llvm/pr-subscribers-backend-risc-v Author: Jim Lin (tclin914) ChangesWe should check the type of x is the same as Fixes #158121. Full diff: https://github.com/llvm/llvm-project/pull/158179.diff 2 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ae9e2fef88673..0203d1a701147 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -15830,7 +15830,8 @@ static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
SDValue N1 = N->getOperand(1);
// fold (sub 0, (setcc x, 0, setlt)) -> (sra x, xlen - 1)
if (isNullConstant(N0) && N1.getOpcode() == ISD::SETCC && N1.hasOneUse() &&
- isNullConstant(N1.getOperand(1))) {
+ isNullConstant(N1.getOperand(1)) &&
+ N1.getValueType() == N1.getOperand(0).getValueType()) {
ISD::CondCode CCVal = cast<CondCodeSDNode>(N1.getOperand(2))->get();
if (CCVal == ISD::SETLT) {
SDLoc DL(N);
diff --git a/llvm/test/CodeGen/RISCV/pr158121.ll b/llvm/test/CodeGen/RISCV/pr158121.ll
new file mode 100644
index 0000000000000..2c018444e9c67
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr158121.ll
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
+
+define i64 @f(ptr %p) {
+; CHECK-LABEL: f:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lb a0, 0(a0)
+; CHECK-NEXT: srai a0, a0, 63
+; CHECK-NEXT: ret
+ %load = load i8, ptr %p, align 1
+ %conv1 = zext i8 %load to i32
+ %cmp = icmp ult i32 127, %conv1
+ %conv2 = zext i1 %cmp to i32
+ %sub = sub nsw i32 0, %conv2
+ %conv3 = sext i32 %sub to i64
+ ret i64 %conv3
+}
|
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
LGTM.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
LGTM
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/186/builds/12402 Here is the relevant piece of the build log for the reference
|
We should check the type of x is the same as
sub
operation. Otherwise the shift amount xlen -1 will exceed the bit size of x.Fixes #158121.