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[RISCV] Check the types are the same for folding (sub 0, (setcc x, 0, setlt)) to (sra x, xlen - 1) #158179

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Merged
merged 1 commit into from
Sep 15, 2025
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[RISCV] Check the types are the same for folding (sub 0, (setcc x, 0, setlt)) to (sra x, xlen - 1) #158179

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3 changes: 2 additions & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -15830,7 +15830,8 @@ static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
SDValue N1 = N->getOperand(1);
// fold (sub 0, (setcc x, 0, setlt)) -> (sra x, xlen - 1)
if (isNullConstant(N0) && N1.getOpcode() == ISD::SETCC && N1.hasOneUse() &&
isNullConstant(N1.getOperand(1))) {
isNullConstant(N1.getOperand(1)) &&
N1.getValueType() == N1.getOperand(0).getValueType()) {
ISD::CondCode CCVal = cast<CondCodeSDNode>(N1.getOperand(2))->get();
if (CCVal == ISD::SETLT) {
SDLoc DL(N);
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17 changes: 17 additions & 0 deletions llvm/test/CodeGen/RISCV/pr158121.ll
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@@ -0,0 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=riscv64 | FileCheck %s

define i64 @f(ptr %p) {
; CHECK-LABEL: f:
; CHECK: # %bb.0:
; CHECK-NEXT: lb a0, 0(a0)
; CHECK-NEXT: srai a0, a0, 63
; CHECK-NEXT: ret
%load = load i8, ptr %p, align 1
%conv1 = zext i8 %load to i32
%cmp = icmp ult i32 127, %conv1
%conv2 = zext i1 %cmp to i32
%sub = sub nsw i32 0, %conv2
%conv3 = sext i32 %sub to i64
ret i64 %conv3
}