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[RISCV] Increase GPRPair Allocation Priority #159169

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[RISCV] Increase GPRPair Allocation Priority #159169

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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVRegisterInfo.td
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Expand Up @@ -358,7 +358,7 @@ let RegAltNameIndices = [ABIRegAltName] in {
}
}

let RegInfos = XLenPairRI, CopyCost = 2 in {
let RegInfos = XLenPairRI, CopyCost = 2, AllocationPriority = 1 in {
def GPRPair : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (add
X10_X11, X12_X13, X14_X15, X16_X17,
X6_X7,
Expand All @@ -373,7 +373,7 @@ def GPRPairNoX0 : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (sub GPRPair
def GPRPairC : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (add
X10_X11, X12_X13, X14_X15, X8_X9
)>;
} // let RegInfos = XLenPairRI, CopyCost = 2
} // let RegInfos = XLenPairRI, CopyCost = 2, AllocationPriority = 1

//===----------------------------------------------------------------------===//
// Floating Point registers
Expand Down
80 changes: 40 additions & 40 deletions llvm/test/CodeGen/RISCV/double-convert.ll
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Expand Up @@ -729,13 +729,13 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_0)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI12_0)(a2)
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI12_0)
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI12_0)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a3)
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI12_0)
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: mv s0, a0
; RV32IZFINXZDINX-NEXT: fle.d s2, a4, s0
; RV32IZFINXZDINX-NEXT: fle.d s2, a2, s0
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lui a3, 524288
; RV32IZFINXZDINX-NEXT: lui a2, 524288
Expand Down Expand Up @@ -981,15 +981,15 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: mv s0, a0
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: fle.d a2, zero, s0
; RV32IZFINXZDINX-NEXT: fle.d a4, zero, s0
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI14_0)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI14_0)(a3)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI14_0)(a3)
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI14_0)
; RV32IZFINXZDINX-NEXT: lw a5, 4(a3)
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a1, a2, a1
; RV32IZFINXZDINX-NEXT: flt.d a2, a4, s0
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
; RV32IZFINXZDINX-NEXT: neg a4, a4
; RV32IZFINXZDINX-NEXT: and a0, a4, a0
; RV32IZFINXZDINX-NEXT: and a1, a4, a1
; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: or a1, a2, a1
Expand Down Expand Up @@ -1650,17 +1650,17 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_w_s_sat_i16:
; RV32IZFINXZDINX: # %bb.0: # %start
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_0)
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI26_1)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI26_0)(a2)
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI26_0)
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI26_1)(a3)
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI26_1)
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI26_0)
; RV32IZFINXZDINX-NEXT: lui a5, %hi(.LCPI26_1)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI26_0)(a3)
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI26_0)
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI26_1)(a5)
; RV32IZFINXZDINX-NEXT: addi a5, a5, %lo(.LCPI26_1)
; RV32IZFINXZDINX-NEXT: lw a5, 4(a5)
; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
; RV32IZFINXZDINX-NEXT: neg a1, a6
; RV32IZFINXZDINX-NEXT: and a0, a1, a0
Expand Down Expand Up @@ -1848,12 +1848,12 @@ define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_wu_s_sat_i16:
; RV32IZFINXZDINX: # %bb.0: # %start
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI28_0)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI28_0)(a2)
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI28_0)
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI28_0)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI28_0)(a3)
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI28_0)
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, zero
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
; RV32IZFINXZDINX-NEXT: ret
;
Expand Down Expand Up @@ -2026,17 +2026,17 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_w_s_sat_i8:
; RV32IZFINXZDINX: # %bb.0: # %start
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI30_0)
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI30_1)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI30_0)(a2)
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI30_0)
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI30_1)(a3)
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI30_1)
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI30_0)
; RV32IZFINXZDINX-NEXT: lui a5, %hi(.LCPI30_1)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI30_0)(a3)
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI30_0)
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI30_1)(a5)
; RV32IZFINXZDINX-NEXT: addi a5, a5, %lo(.LCPI30_1)
; RV32IZFINXZDINX-NEXT: lw a5, 4(a5)
; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
; RV32IZFINXZDINX-NEXT: neg a1, a6
; RV32IZFINXZDINX-NEXT: and a0, a1, a0
Expand Down Expand Up @@ -2224,12 +2224,12 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_wu_s_sat_i8:
; RV32IZFINXZDINX: # %bb.0: # %start
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI32_0)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI32_0)(a2)
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI32_0)
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI32_0)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI32_0)(a3)
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI32_0)
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, zero
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
; RV32IZFINXZDINX-NEXT: ret
;
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/double-imm.ll
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Expand Up @@ -54,11 +54,11 @@ define double @double_imm_op(double %a) nounwind {
;
; CHECKRV32ZDINX-LABEL: double_imm_op:
; CHECKRV32ZDINX: # %bb.0:
; CHECKRV32ZDINX-NEXT: lui a2, %hi(.LCPI1_0)
; CHECKRV32ZDINX-NEXT: lw a4, %lo(.LCPI1_0)(a2)
; CHECKRV32ZDINX-NEXT: addi a2, a2, %lo(.LCPI1_0)
; CHECKRV32ZDINX-NEXT: lw a5, 4(a2)
; CHECKRV32ZDINX-NEXT: fadd.d a0, a0, a4
; CHECKRV32ZDINX-NEXT: lui a3, %hi(.LCPI1_0)
; CHECKRV32ZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a3)
; CHECKRV32ZDINX-NEXT: addi a3, a3, %lo(.LCPI1_0)
; CHECKRV32ZDINX-NEXT: lw a3, 4(a3)
; CHECKRV32ZDINX-NEXT: fadd.d a0, a0, a2
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: double_imm_op:
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
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Expand Up @@ -286,15 +286,15 @@ define double @sincos_f64(double %a) nounwind strictfp {
; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: mv s0, a1
; RV32IZFINXZDINX-NEXT: mv s1, a0
; RV32IZFINXZDINX-NEXT: mv s2, a1
; RV32IZFINXZDINX-NEXT: mv s3, a0
; RV32IZFINXZDINX-NEXT: call sin
; RV32IZFINXZDINX-NEXT: mv s2, a0
; RV32IZFINXZDINX-NEXT: mv s3, a1
; RV32IZFINXZDINX-NEXT: mv a0, s1
; RV32IZFINXZDINX-NEXT: mv a1, s0
; RV32IZFINXZDINX-NEXT: mv s0, a0
; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: mv a0, s3
; RV32IZFINXZDINX-NEXT: mv a1, s2
; RV32IZFINXZDINX-NEXT: call cos
; RV32IZFINXZDINX-NEXT: fadd.d a0, s2, a0
; RV32IZFINXZDINX-NEXT: fadd.d a0, s0, a0
; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/RISCV/double-intrinsics.ll
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Expand Up @@ -241,15 +241,15 @@ define double @sincos_f64(double %a) nounwind {
; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: mv s0, a1
; RV32IZFINXZDINX-NEXT: mv s1, a0
; RV32IZFINXZDINX-NEXT: mv s2, a1
; RV32IZFINXZDINX-NEXT: mv s3, a0
; RV32IZFINXZDINX-NEXT: call sin
; RV32IZFINXZDINX-NEXT: mv s2, a0
; RV32IZFINXZDINX-NEXT: mv s3, a1
; RV32IZFINXZDINX-NEXT: mv a0, s1
; RV32IZFINXZDINX-NEXT: mv a1, s0
; RV32IZFINXZDINX-NEXT: mv s0, a0
; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: mv a0, s3
; RV32IZFINXZDINX-NEXT: mv a1, s2
; RV32IZFINXZDINX-NEXT: call cos
; RV32IZFINXZDINX-NEXT: fadd.d a0, s2, a0
; RV32IZFINXZDINX-NEXT: fadd.d a0, s0, a0
; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/double-mem.ll
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Expand Up @@ -179,12 +179,12 @@ define dso_local double @fld_fsd_constant(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fld_fsd_constant:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: lui a2, 912092
; RV32IZFINXZDINX-NEXT: lw a4, -273(a2)
; RV32IZFINXZDINX-NEXT: lw a5, -269(a2)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a4
; RV32IZFINXZDINX-NEXT: sw a0, -273(a2)
; RV32IZFINXZDINX-NEXT: sw a1, -269(a2)
; RV32IZFINXZDINX-NEXT: lui a4, 912092
; RV32IZFINXZDINX-NEXT: lw a2, -273(a4)
; RV32IZFINXZDINX-NEXT: lw a3, -269(a4)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: sw a0, -273(a4)
; RV32IZFINXZDINX-NEXT: sw a1, -269(a4)
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fld_fsd_constant:
Expand All @@ -198,10 +198,10 @@ define dso_local double @fld_fsd_constant(double %a) nounwind {
;
; RV32IZFINXZDINXZILSD-LABEL: fld_fsd_constant:
; RV32IZFINXZDINXZILSD: # %bb.0:
; RV32IZFINXZDINXZILSD-NEXT: lui a2, 912092
; RV32IZFINXZDINXZILSD-NEXT: ld a4, -273(a2)
; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, a4
; RV32IZFINXZDINXZILSD-NEXT: sd a0, -273(a2)
; RV32IZFINXZDINXZILSD-NEXT: lui a4, 912092
; RV32IZFINXZDINXZILSD-NEXT: ld a2, -273(a4)
; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, a2
; RV32IZFINXZDINXZILSD-NEXT: sd a0, -273(a4)
; RV32IZFINXZDINXZILSD-NEXT: ret
%1 = inttoptr i32 3735928559 to ptr
%2 = load volatile double, ptr %1
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/double-previous-failure.ll
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Expand Up @@ -50,18 +50,18 @@ define i32 @main() nounwind {
; RV32IZFINXZDINX-NEXT: lui a1, 262144
; RV32IZFINXZDINX-NEXT: li a0, 0
; RV32IZFINXZDINX-NEXT: call test
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_0)(a2)
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI1_0)
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
; RV32IZFINXZDINX-NEXT: flt.d a2, a0, a4
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI1_0)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a3)
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI1_0)
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
; RV32IZFINXZDINX-NEXT: flt.d a2, a0, a2
; RV32IZFINXZDINX-NEXT: bnez a2, .LBB1_3
; RV32IZFINXZDINX-NEXT: # %bb.1: # %entry
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_1)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_1)(a2)
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI1_1)
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
; RV32IZFINXZDINX-NEXT: flt.d a0, a4, a0
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI1_1)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_1)(a3)
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI1_1)
; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: bnez a0, .LBB1_3
; RV32IZFINXZDINX-NEXT: # %bb.2: # %if.end
; RV32IZFINXZDINX-NEXT: call exit
Expand Down
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