[CodeGen][NewPM] Port ReachingDefAnalysis to new pass manager.
#159572
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@llvm/pr-subscribers-backend-risc-v @llvm/pr-subscribers-backend-arm Author: Mikhail Gudim (mgudim) ChangesIn this commit: Patch is 52.32 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/159572.diff 14 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/ExecutionDomainFix.h b/llvm/include/llvm/CodeGen/ExecutionDomainFix.h
index 6846a3dd84f7c..81994d932cc8a 100644
--- a/llvm/include/llvm/CodeGen/ExecutionDomainFix.h
+++ b/llvm/include/llvm/CodeGen/ExecutionDomainFix.h
@@ -133,7 +133,7 @@ class ExecutionDomainFix : public MachineFunctionPass {
using OutRegsInfoMap = SmallVector<LiveRegsDVInfo, 4>;
OutRegsInfoMap MBBOutRegsInfos;
- ReachingDefAnalysis *RDA = nullptr;
+ ReachingDefInfo *RDI = nullptr;
public:
ExecutionDomainFix(char &PassID, const TargetRegisterClass &RC)
@@ -141,7 +141,7 @@ class ExecutionDomainFix : public MachineFunctionPass {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll();
- AU.addRequired<ReachingDefAnalysis>();
+ AU.addRequired<ReachingDefInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
diff --git a/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h b/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
index 41ea462201ee5..3c152b56fe05b 100644
--- a/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
+++ b/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
@@ -26,6 +26,7 @@
#include "llvm/ADT/TinyPtrVector.h"
#include "llvm/CodeGen/LoopTraversal.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/InitializePasses.h"
namespace llvm {
@@ -110,7 +111,7 @@ class MBBReachingDefsInfo {
};
/// This class provides the reaching def analysis.
-class ReachingDefAnalysis : public MachineFunctionPass {
+class ReachingDefInfo {
private:
MachineFunction *MF = nullptr;
const TargetRegisterInfo *TRI = nullptr;
@@ -156,24 +157,16 @@ class ReachingDefAnalysis : public MachineFunctionPass {
using BlockSet = SmallPtrSetImpl<MachineBasicBlock*>;
public:
- static char ID; // Pass identification, replacement for typeid
+ ReachingDefInfo();
+ ReachingDefInfo(ReachingDefInfo &&);
+ ~ReachingDefInfo();
+ /// Handle invalidation explicitly.
+ bool invalidate(MachineFunction &F, const PreservedAnalyses &PA,
+ MachineFunctionAnalysisManager::Invalidator &);
- ReachingDefAnalysis() : MachineFunctionPass(ID) {
- initializeReachingDefAnalysisPass(*PassRegistry::getPassRegistry());
- }
- void releaseMemory() override;
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.setPreservesAll();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
-
- void printAllReachingDefs(MachineFunction &MF);
- bool runOnMachineFunction(MachineFunction &MF) override;
-
- MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().setNoVRegs().setTracksLiveness();
- }
+ void run(MachineFunction &mf);
+ void print(raw_ostream &OS);
+ void releaseMemory();
/// Re-run the analysis.
void reset();
@@ -319,6 +312,50 @@ class ReachingDefAnalysis : public MachineFunctionPass {
MachineInstr *getReachingLocalMIDef(MachineInstr *MI, Register Reg) const;
};
+class ReachingDefAnalysis
+ : public AnalysisInfoMixin<ReachingDefAnalysis> {
+ friend AnalysisInfoMixin<ReachingDefAnalysis>;
+ static AnalysisKey Key;
+
+public:
+ using Result = ReachingDefInfo;
+
+ Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
+/// Printer pass for the \c ReachingDefInfo results.
+class ReachingDefPrinterPass
+ : public PassInfoMixin<ReachingDefPrinterPass> {
+ raw_ostream &OS;
+
+public:
+ explicit ReachingDefPrinterPass(raw_ostream &OS) : OS(OS) {}
+
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+
+ static bool isRequired() { return true; }
+};
+
+class ReachingDefInfoWrapperPass : public MachineFunctionPass {
+ ReachingDefInfo RDI;
+
+public:
+ static char ID;
+
+ ReachingDefInfoWrapperPass();
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+
+ bool runOnMachineFunction(MachineFunction &F) override;
+
+ void releaseMemory() override { RDI.releaseMemory(); }
+
+ ReachingDefInfo &getRDI() { return RDI; }
+
+ const ReachingDefInfo &getRDI() const { return RDI; }
+};
+
} // namespace llvm
#endif // LLVM_CODEGEN_REACHINGDEFANALYSIS_H
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index a99b0ff188ea8..88272f053c114 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -264,7 +264,7 @@ LLVM_ABI void initializePromoteLegacyPassPass(PassRegistry &);
LLVM_ABI void initializeRABasicPass(PassRegistry &);
LLVM_ABI void initializePseudoProbeInserterPass(PassRegistry &);
LLVM_ABI void initializeRAGreedyLegacyPass(PassRegistry &);
-LLVM_ABI void initializeReachingDefAnalysisPass(PassRegistry &);
+LLVM_ABI void initializeReachingDefInfoWrapperPassPass(PassRegistry &);
LLVM_ABI void initializeReassociateLegacyPassPass(PassRegistry &);
LLVM_ABI void
initializeRegAllocEvictionAdvisorAnalysisLegacyPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index bee210678f84f..c3cf18d6f2345 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -84,6 +84,8 @@ MACHINE_FUNCTION_ANALYSIS("machine-uniformity", MachineUniformityAnalysis())
MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC))
MACHINE_FUNCTION_ANALYSIS("regalloc-evict", RegAllocEvictionAdvisorAnalysis())
MACHINE_FUNCTION_ANALYSIS("regalloc-priority", RegAllocPriorityAdvisorAnalysis())
+MACHINE_FUNCTION_ANALYSIS("reaching-def",
+ReachingDefAnalysis())
MACHINE_FUNCTION_ANALYSIS("slot-indexes", SlotIndexesAnalysis())
MACHINE_FUNCTION_ANALYSIS("spill-code-placement", SpillPlacementAnalysis())
MACHINE_FUNCTION_ANALYSIS("virtregmap", VirtRegMapAnalysis())
@@ -96,8 +98,7 @@ MACHINE_FUNCTION_ANALYSIS("virtregmap", VirtRegMapAnalysis())
// MachinePostDominatorTreeAnalysis())
// MACHINE_FUNCTION_ANALYSIS("machine-region-info",
// MachineRegionInfoPassAnalysis())
-// MACHINE_FUNCTION_ANALYSIS("reaching-def",
-// ReachingDefAnalysisAnalysis()) MACHINE_FUNCTION_ANALYSIS("gc-analysis",
+// MACHINE_FUNCTION_ANALYSIS("gc-analysis",
// GCMachineCodeAnalysisPass())
#undef MACHINE_FUNCTION_ANALYSIS
@@ -153,6 +154,7 @@ MACHINE_FUNCTION_PASS("print<machine-uniformity>",
MachineUniformityPrinterPass(errs()))
MACHINE_FUNCTION_PASS("print<slot-indexes>", SlotIndexesPrinterPass(errs()))
MACHINE_FUNCTION_PASS("print<virtregmap>", VirtRegMapPrinterPass(errs()))
+MACHINE_FUNCTION_PASS("print<reaching-def>", ReachingDefPrinterPass(errs()))
MACHINE_FUNCTION_PASS("process-imp-defs", ProcessImplicitDefsPass())
MACHINE_FUNCTION_PASS("prolog-epilog", PrologEpilogInserterPass())
MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass())
diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp
index 205020af1b30d..28e67283b76f0 100644
--- a/llvm/lib/CodeGen/BreakFalseDeps.cpp
+++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp
@@ -46,7 +46,7 @@ class BreakFalseDeps : public MachineFunctionPass {
/// Storage for register unit liveness.
LivePhysRegs LiveRegSet;
- ReachingDefAnalysis *RDA = nullptr;
+ ReachingDefInfo *RDI = nullptr;
public:
static char ID; // Pass identification, replacement for typeid
@@ -57,7 +57,7 @@ class BreakFalseDeps : public MachineFunctionPass {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll();
- AU.addRequired<ReachingDefAnalysis>();
+ AU.addRequired<ReachingDefInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -101,7 +101,7 @@ class BreakFalseDeps : public MachineFunctionPass {
char BreakFalseDeps::ID = 0;
INITIALIZE_PASS_BEGIN(BreakFalseDeps, DEBUG_TYPE, "BreakFalseDeps", false, false)
-INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
+INITIALIZE_PASS_DEPENDENCY(ReachingDefInfoWrapperPass)
INITIALIZE_PASS_END(BreakFalseDeps, DEBUG_TYPE, "BreakFalseDeps", false, false)
FunctionPass *llvm::createBreakFalseDeps() { return new BreakFalseDeps(); }
@@ -153,7 +153,7 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
unsigned MaxClearanceReg = OriginalReg;
ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
for (MCPhysReg Reg : Order) {
- unsigned Clearance = RDA->getClearance(MI, Reg);
+ unsigned Clearance = RDI->getClearance(MI, Reg);
if (Clearance <= MaxClearance)
continue;
MaxClearance = Clearance;
@@ -173,7 +173,7 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
unsigned Pref) {
MCRegister Reg = MI->getOperand(OpIdx).getReg().asMCReg();
- unsigned Clearance = RDA->getClearance(MI, Reg);
+ unsigned Clearance = RDI->getClearance(MI, Reg);
LLVM_DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref);
if (Pref > Clearance) {
@@ -282,7 +282,7 @@ bool BreakFalseDeps::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
TII = MF->getSubtarget().getInstrInfo();
TRI = MF->getSubtarget().getRegisterInfo();
- RDA = &getAnalysis<ReachingDefAnalysis>();
+ RDI = &getAnalysis<ReachingDefInfoWrapperPass>().getRDI();
RegClassInfo.runOnMachineFunction(mf, /*Rev=*/true);
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 989cf4c4796ae..9e0cb3bf44906 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -112,6 +112,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeProcessImplicitDefsLegacyPass(Registry);
initializeRABasicPass(Registry);
initializeRAGreedyLegacyPass(Registry);
+ initializeReachingDefInfoWrapperPassPass(Registry);
initializeRegAllocFastPass(Registry);
initializeRegUsageInfoCollectorLegacyPass(Registry);
initializeRegUsageInfoPropagationLegacyPass(Registry);
diff --git a/llvm/lib/CodeGen/ExecutionDomainFix.cpp b/llvm/lib/CodeGen/ExecutionDomainFix.cpp
index e540c67cadbeb..0ce095ab1d804 100644
--- a/llvm/lib/CodeGen/ExecutionDomainFix.cpp
+++ b/llvm/lib/CodeGen/ExecutionDomainFix.cpp
@@ -337,9 +337,9 @@ void ExecutionDomainFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
}
// Sorted insertion.
// Enables giving priority to the latest domains during merging.
- const int Def = RDA->getReachingDef(mi, RC->getRegister(rx));
+ const int Def = RDI->getReachingDef(mi, RC->getRegister(rx));
auto I = partition_point(Regs, [&](int I) {
- return RDA->getReachingDef(mi, RC->getRegister(I)) <= Def;
+ return RDI->getReachingDef(mi, RC->getRegister(I)) <= Def;
});
Regs.insert(I, rx);
}
@@ -435,7 +435,7 @@ bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) {
if (!anyregs)
return false;
- RDA = &getAnalysis<ReachingDefAnalysis>();
+ RDI = &getAnalysis<ReachingDefInfoWrapperPass>().getRDI();
// Initialize the AliasMap on the first use.
if (AliasMap.empty()) {
diff --git a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
index a589ef761dd79..6ead755e98cb9 100644
--- a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
+++ b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
@@ -20,14 +20,55 @@ using namespace llvm;
#define DEBUG_TYPE "reaching-defs-analysis"
-static cl::opt<bool> PrintAllReachingDefs("print-all-reaching-defs", cl::Hidden,
- cl::desc("Used for test purpuses"),
- cl::Hidden);
+AnalysisKey ReachingDefAnalysis::Key;
-char ReachingDefAnalysis::ID = 0;
-INITIALIZE_PASS(ReachingDefAnalysis, DEBUG_TYPE, "ReachingDefAnalysis", false,
+ReachingDefAnalysis::Result
+ReachingDefAnalysis::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ ReachingDefInfo RDI;
+ RDI.run(MF);
+ return RDI;
+}
+
+PreservedAnalyses
+ReachingDefPrinterPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ auto &RDI = MFAM.getResult<ReachingDefAnalysis>(MF);
+ OS << "Reaching definitions for for machine function: " << MF.getName()
+ << '\n';
+ RDI.print(OS);
+ return PreservedAnalyses::all();
+}
+
+INITIALIZE_PASS(ReachingDefInfoWrapperPass, DEBUG_TYPE, "Reaching Definitions Analysis", false,
true)
+char ReachingDefInfoWrapperPass::ID = 0;
+
+ReachingDefInfoWrapperPass::ReachingDefInfoWrapperPass() : MachineFunctionPass(ID) {
+ initializeReachingDefInfoWrapperPassPass(*PassRegistry::getPassRegistry());
+}
+
+ReachingDefInfo::ReachingDefInfo() = default;
+ReachingDefInfo::ReachingDefInfo(ReachingDefInfo &&) = default;
+ReachingDefInfo::~ReachingDefInfo() = default;
+
+bool ReachingDefInfo::invalidate(
+ MachineFunction &MF, const PreservedAnalyses &PA,
+ MachineFunctionAnalysisManager::Invalidator &) {
+ // Check whether the analysis, all analyses on machine functions, or the
+ // machine function's CFG have been preserved.
+ auto PAC = PA.getChecker<ReachingDefAnalysis>();
+ return !PAC.preserved() &&
+ !PAC.preservedSet<AllAnalysesOn<MachineFunction>>() &&
+ !PAC.preservedSet<CFGAnalyses>();
+}
+
+void ReachingDefInfoWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.setPreservesAll();
+ MachineFunctionPass::getAnalysisUsage(AU);
+}
+
static bool isValidReg(const MachineOperand &MO) {
return MO.isReg() && MO.getReg();
}
@@ -64,7 +105,7 @@ static bool isFIDef(const MachineInstr &MI, int FrameIndex,
return false;
}
-void ReachingDefAnalysis::enterBasicBlock(MachineBasicBlock *MBB) {
+void ReachingDefInfo::enterBasicBlock(MachineBasicBlock *MBB) {
unsigned MBBNumber = MBB->getNumber();
assert(MBBNumber < MBBReachingDefs.numBlockIDs() &&
"Unexpected basic block number.");
@@ -116,7 +157,7 @@ void ReachingDefAnalysis::enterBasicBlock(MachineBasicBlock *MBB) {
MBBReachingDefs.append(MBBNumber, Unit, LiveRegs[Unit]);
}
-void ReachingDefAnalysis::leaveBasicBlock(MachineBasicBlock *MBB) {
+void ReachingDefInfo::leaveBasicBlock(MachineBasicBlock *MBB) {
assert(!LiveRegs.empty() && "Must enter basic block first.");
unsigned MBBNumber = MBB->getNumber();
assert(MBBNumber < MBBOutRegsInfos.size() &&
@@ -134,7 +175,7 @@ void ReachingDefAnalysis::leaveBasicBlock(MachineBasicBlock *MBB) {
LiveRegs.clear();
}
-void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
+void ReachingDefInfo::processDefs(MachineInstr *MI) {
assert(!MI->isDebugInstr() && "Won't process debug instructions");
unsigned MBBNumber = MI->getParent()->getNumber();
@@ -167,7 +208,7 @@ void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
++CurInstr;
}
-void ReachingDefAnalysis::reprocessBasicBlock(MachineBasicBlock *MBB) {
+void ReachingDefInfo::reprocessBasicBlock(MachineBasicBlock *MBB) {
unsigned MBBNumber = MBB->getNumber();
assert(MBBNumber < MBBReachingDefs.numBlockIDs() &&
"Unexpected basic block number.");
@@ -212,7 +253,7 @@ void ReachingDefAnalysis::reprocessBasicBlock(MachineBasicBlock *MBB) {
}
}
-void ReachingDefAnalysis::processBasicBlock(
+void ReachingDefInfo::processBasicBlock(
const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
MachineBasicBlock *MBB = TraversedMBB.MBB;
LLVM_DEBUG(dbgs() << printMBBReference(*MBB)
@@ -232,12 +273,22 @@ void ReachingDefAnalysis::processBasicBlock(
leaveBasicBlock(MBB);
}
-void ReachingDefAnalysis::printAllReachingDefs(MachineFunction &MF) {
- dbgs() << "RDA results for " << MF.getName() << "\n";
+void ReachingDefInfo::run(MachineFunction &mf) {
+ MF = &mf;
+ const TargetSubtargetInfo &STI = MF->getSubtarget();
+ TRI = STI.getRegisterInfo();
+ TII = STI.getInstrInfo();
+ LLVM_DEBUG(dbgs() << "********** REACHING DEFINITION ANALYSIS **********\n");
+ init();
+ traverse();
+}
+
+void ReachingDefInfo::print(raw_ostream &OS) {
+ OS << "RDA results for " << MF->getName() << "\n";
int Num = 0;
DenseMap<MachineInstr *, int> InstToNumMap;
SmallPtrSet<MachineInstr *, 2> Defs;
- for (MachineBasicBlock &MBB : MF) {
+ for (MachineBasicBlock &MBB : *MF) {
for (MachineInstr &MI : MBB) {
for (MachineOperand &MO : MI.operands()) {
Register Reg;
@@ -256,37 +307,29 @@ void ReachingDefAnalysis::printAllReachingDefs(MachineFunction &MF) {
continue;
Defs.clear();
getGlobalReachingDefs(&MI, Reg, Defs);
- MO.print(dbgs(), TRI);
+ MO.print(OS, TRI);
SmallVector<int, 0> Nums;
for (MachineInstr *Def : Defs)
Nums.push_back(InstToNumMap[Def]);
llvm::sort(Nums);
- dbgs() << ":{ ";
+ OS << ":{ ";
for (int Num : Nums)
- dbgs() << Num << " ";
- dbgs() << "}\n";
+ OS << Num << " ";
+ OS << "}\n";
}
- dbgs() << Num << ": " << MI << "\n";
+ OS << Num << ": " << MI << "\n";
InstToNumMap[&MI] = Num;
++Num;
}
}
}
-bool ReachingDefAnalysis::runOnMachineFunction(MachineFunction &mf) {
- MF = &mf;
- const TargetSubtargetInfo &STI = MF->getSubtarget();
- TRI = STI.getRegisterInfo();
- TII = STI.getInstrInfo();
- LLVM_DEBUG(dbgs() << "********** REACHING DEFINITION ANALYSIS **********\n");
- init();
- traverse();
- if (PrintAllReachingDefs)
- printAllReachingDefs(*MF);
+bool ReachingDefInfoWrapperPass::runOnMachineFunction(MachineFunction &mf) {
+ RDI.run(mf);
return false;
}
-void ReachingDefAnalysis::releaseMemory() {
+void ReachingDefInfo::releaseMemory() {
// Clear the internal vectors.
MBBOutRegsInfos.clear();
MBBReachingDefs.clear();
@@ -295,13 +338,13 @@ void ReachingDefAnalysis::releaseMemory() {
LiveRegs.clear();
}
-void ReachingDefAnalysis::reset() {
+void ReachingDefInfo::reset() {
releaseMemory();
init();
traverse();
}
-void ReachingDefAnalysis::init() {
+void ReachingDefInfo::init() {
NumRegUnits = TRI->getNumRegUnits();
NumStackObjects = MF->getFrameInfo().getNumObjects();
ObjectIndexBegin = MF->getFrameInfo().getObjectIndexBegin();
@@ -312,7 +355,7 @@ void ReachingDefAnalysis::init() {
TraversedMBBOrder = Traversal.traverse(*MF);
}
-void ReachingDefAnalysis::traverse() {
+void ReachingDefInfo::traverse() {
// Traverse the basic blocks.
for (LoopTraversal::TraversedMBBInfo TraversedMBB : TraversedMBBOrder)
processBasicBlock(TraversedMBB);
@@ -331,7 +374,7 @@ void ReachingDefAnalysis::traverse() {
#endif
}
-int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, Register Reg) const {
+int ReachingDefInfo::getReachingDef(MachineInstr *MI, Register Reg) const {
assert(InstIds.count(MI) && "Unexpected machine instuction.");
int InstId = InstIds.lookup(MI);
int DefRes = ReachingDefDefaultVal;
@@ -367,14 +410,14 @@ int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, Register Reg) const {
return LatestDef;
}
-MachineInstr *ReachingDefAnalysis::getReachingLocalMIDef(MachineInstr *MI,
+MachineInstr *ReachingDefInfo::getReachingLocalMIDef(MachineInstr *MI,
Register Reg) const {
return hasLocalDefBefore(MI, Reg)
? getInstFromId(MI->getParent(), getReachingDef(MI, Reg))
: nullptr;
}
-bool ReachingDefAnalysis::hasSameReachingDef(MachineInstr *A, MachineInstr *B,
+bool ReachingDefInfo::hasSameReachingDef(MachineInstr *A, MachineInstr *B,
Register Reg) const {
MachineBasicBlock *ParentA = A->getParent();
MachineBasicBlock *ParentB = B->getParent();
@@ -384,7 +427,7 @@ bool ReachingDefAnalysis::hasSameReachingDef(MachineInstr *A, MachineInstr *B,
return getReachingDef(A, Reg) == getReachingDef(B, Reg);
}
-MachineInstr *ReachingDefAnalysis::getInstFromId(MachineBasicBlock *MBB,
+MachineInstr *ReachingDefInfo::getInstFromId(MachineBasicBlock *MBB,
int InstId) const {
assert(static_cast<size_t>(MBB->getNumber()) <
MBBReachingDefs.numBlockIDs() &&
@@ -404,17 +447,17 @@ MachineInstr *ReachingDefAnalysis::getInstFromId(MachineBasicBlock *MBB,
return nullptr;
}
-int ReachingDefAnalysis::getClearance(MachineInstr *MI, Register Reg) const {
+in...
[truncated]
|
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
added 2 commits
September 18, 2025 09:19
In this commit: (1) Added new pass manager support for `ReachingDefAnalysis`. (2) Added printer pass. (3) Make old pass manager use `ReachingDefInfoWrapperPass`
paperchalice
approved these changes
Sep 19, 2025
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In this commit:
(1) Added new pass manager support for
ReachingDefAnalysis.(2) Added printer pass.
(3) Make old pass manager use
ReachingDefInfoWrapperPass