[CodeGen][NewPM] Port ReachingDefAnalysis to new pass manager.

llvm/include/llvm/CodeGen/ExecutionDomainFix.h

@@ -133,15 +133,15 @@ class ExecutionDomainFix : public MachineFunctionPass {
   using OutRegsInfoMap = SmallVector<LiveRegsDVInfo, 4>;
   OutRegsInfoMap MBBOutRegsInfos;
 
-  ReachingDefAnalysis *RDA = nullptr;
+  ReachingDefInfo *RDI = nullptr;
 
 public:
   ExecutionDomainFix(char &PassID, const TargetRegisterClass &RC)
       : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesAll();
-    AU.addRequired<ReachingDefAnalysis>();
+    AU.addRequired<ReachingDefInfoWrapperPass>();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 

llvm/include/llvm/CodeGen/ReachingDefAnalysis.h

@@ -26,6 +26,7 @@
 #include "llvm/ADT/TinyPtrVector.h"
 #include "llvm/CodeGen/LoopTraversal.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
 #include "llvm/InitializePasses.h"
 
 namespace llvm {
@@ -110,7 +111,7 @@ class MBBReachingDefsInfo {
 };
 
 /// This class provides the reaching def analysis.
-class ReachingDefAnalysis : public MachineFunctionPass {
+class ReachingDefInfo {
 private:
   MachineFunction *MF = nullptr;
   const TargetRegisterInfo *TRI = nullptr;
@@ -156,24 +157,16 @@ class ReachingDefAnalysis : public MachineFunctionPass {
   using BlockSet = SmallPtrSetImpl<MachineBasicBlock*>;
 
 public:
-  static char ID; // Pass identification, replacement for typeid
+  ReachingDefInfo();
+  ReachingDefInfo(ReachingDefInfo &&);
+  ~ReachingDefInfo();
+  /// Handle invalidation explicitly.
+  bool invalidate(MachineFunction &F, const PreservedAnalyses &PA,
+                  MachineFunctionAnalysisManager::Invalidator &);
 
-  ReachingDefAnalysis() : MachineFunctionPass(ID) {
-    initializeReachingDefAnalysisPass(*PassRegistry::getPassRegistry());
-  }
-  void releaseMemory() override;
-
-  void getAnalysisUsage(AnalysisUsage &AU) const override {
-    AU.setPreservesAll();
-    MachineFunctionPass::getAnalysisUsage(AU);
-  }
-
-  void printAllReachingDefs(MachineFunction &MF);
-  bool runOnMachineFunction(MachineFunction &MF) override;
-
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().setNoVRegs().setTracksLiveness();
-  }
+  void run(MachineFunction &mf);
+  void print(raw_ostream &OS);
+  void releaseMemory();
 
   /// Re-run the analysis.
   void reset();
@@ -319,6 +312,46 @@ class ReachingDefAnalysis : public MachineFunctionPass {
   MachineInstr *getReachingLocalMIDef(MachineInstr *MI, Register Reg) const;
 };
 
+class ReachingDefAnalysis : public AnalysisInfoMixin<ReachingDefAnalysis> {
+  friend AnalysisInfoMixin<ReachingDefAnalysis>;
+  static AnalysisKey Key;
+
+public:
+  using Result = ReachingDefInfo;
+
+  Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
+/// Printer pass for the \c ReachingDefInfo results.
+class ReachingDefPrinterPass : public PassInfoMixin<ReachingDefPrinterPass> {
+  raw_ostream &OS;
+
+public:
+  explicit ReachingDefPrinterPass(raw_ostream &OS) : OS(OS) {}
+
+  PreservedAnalyses run(MachineFunction &MF,
+                        MachineFunctionAnalysisManager &MFAM);
+
+  static bool isRequired() { return true; }
+};
+
+class ReachingDefInfoWrapperPass : public MachineFunctionPass {
+  ReachingDefInfo RDI;
+
+public:
+  static char ID;
+
+  ReachingDefInfoWrapperPass();
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override;
+  MachineFunctionProperties getRequiredProperties() const override;
+  bool runOnMachineFunction(MachineFunction &F) override;
+  void releaseMemory() override { RDI.releaseMemory(); }
+
+  ReachingDefInfo &getRDI() { return RDI; }
+  const ReachingDefInfo &getRDI() const { return RDI; }
+};
+
 } // namespace llvm
 
 #endif // LLVM_CODEGEN_REACHINGDEFANALYSIS_H

llvm/include/llvm/InitializePasses.h

@@ -264,7 +264,7 @@ LLVM_ABI void initializePromoteLegacyPassPass(PassRegistry &);
 LLVM_ABI void initializeRABasicPass(PassRegistry &);
 LLVM_ABI void initializePseudoProbeInserterPass(PassRegistry &);
 LLVM_ABI void initializeRAGreedyLegacyPass(PassRegistry &);
-LLVM_ABI void initializeReachingDefAnalysisPass(PassRegistry &);
+LLVM_ABI void initializeReachingDefInfoWrapperPassPass(PassRegistry &);
 LLVM_ABI void initializeReassociateLegacyPassPass(PassRegistry &);
 LLVM_ABI void
 initializeRegAllocEvictionAdvisorAnalysisLegacyPass(PassRegistry &);

llvm/include/llvm/Passes/MachinePassRegistry.def

@@ -82,6 +82,7 @@ MACHINE_FUNCTION_ANALYSIS("machine-post-dom-tree",
 MACHINE_FUNCTION_ANALYSIS("machine-trace-metrics", MachineTraceMetricsAnalysis())
 MACHINE_FUNCTION_ANALYSIS("machine-uniformity", MachineUniformityAnalysis())
 MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC))
+MACHINE_FUNCTION_ANALYSIS("reaching-def", ReachingDefAnalysis())
 MACHINE_FUNCTION_ANALYSIS("regalloc-evict", RegAllocEvictionAdvisorAnalysis())
 MACHINE_FUNCTION_ANALYSIS("regalloc-priority", RegAllocPriorityAdvisorAnalysis())
 MACHINE_FUNCTION_ANALYSIS("slot-indexes", SlotIndexesAnalysis())
@@ -96,8 +97,7 @@ MACHINE_FUNCTION_ANALYSIS("virtregmap", VirtRegMapAnalysis())
 // MachinePostDominatorTreeAnalysis())
 // MACHINE_FUNCTION_ANALYSIS("machine-region-info",
 // MachineRegionInfoPassAnalysis())
-// MACHINE_FUNCTION_ANALYSIS("reaching-def",
-// ReachingDefAnalysisAnalysis()) MACHINE_FUNCTION_ANALYSIS("gc-analysis",
+// MACHINE_FUNCTION_ANALYSIS("gc-analysis",
 // GCMachineCodeAnalysisPass())
 #undef MACHINE_FUNCTION_ANALYSIS
 
@@ -151,6 +151,7 @@ MACHINE_FUNCTION_PASS("print<machine-post-dom-tree>",
                       MachinePostDominatorTreePrinterPass(errs()))
 MACHINE_FUNCTION_PASS("print<machine-uniformity>",
                       MachineUniformityPrinterPass(errs()))
+MACHINE_FUNCTION_PASS("print<reaching-def>", ReachingDefPrinterPass(errs()))
 MACHINE_FUNCTION_PASS("print<slot-indexes>", SlotIndexesPrinterPass(errs()))
 MACHINE_FUNCTION_PASS("print<virtregmap>", VirtRegMapPrinterPass(errs()))
 MACHINE_FUNCTION_PASS("process-imp-defs", ProcessImplicitDefsPass())

llvm/lib/CodeGen/BreakFalseDeps.cpp

@@ -46,7 +46,7 @@ class BreakFalseDeps : public MachineFunctionPass {
   /// Storage for register unit liveness.
   LivePhysRegs LiveRegSet;
 
-  ReachingDefAnalysis *RDA = nullptr;
+  ReachingDefInfo *RDI = nullptr;
 
 public:
   static char ID; // Pass identification, replacement for typeid
@@ -57,7 +57,7 @@ class BreakFalseDeps : public MachineFunctionPass {
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesAll();
-    AU.addRequired<ReachingDefAnalysis>();
+    AU.addRequired<ReachingDefInfoWrapperPass>();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
@@ -101,7 +101,7 @@ class BreakFalseDeps : public MachineFunctionPass {
 
 char BreakFalseDeps::ID = 0;
 INITIALIZE_PASS_BEGIN(BreakFalseDeps, DEBUG_TYPE, "BreakFalseDeps", false, false)
-INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
+INITIALIZE_PASS_DEPENDENCY(ReachingDefInfoWrapperPass)
 INITIALIZE_PASS_END(BreakFalseDeps, DEBUG_TYPE, "BreakFalseDeps", false, false)
 
 FunctionPass *llvm::createBreakFalseDeps() { return new BreakFalseDeps(); }
@@ -153,7 +153,7 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
   unsigned MaxClearanceReg = OriginalReg;
   ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
   for (MCPhysReg Reg : Order) {
-    unsigned Clearance = RDA->getClearance(MI, Reg);
+    unsigned Clearance = RDI->getClearance(MI, Reg);
     if (Clearance <= MaxClearance)
       continue;
     MaxClearance = Clearance;
@@ -173,7 +173,7 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
 bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
                                            unsigned Pref) {
   MCRegister Reg = MI->getOperand(OpIdx).getReg().asMCReg();
-  unsigned Clearance = RDA->getClearance(MI, Reg);
+  unsigned Clearance = RDI->getClearance(MI, Reg);
   LLVM_DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref);
 
   if (Pref > Clearance) {
@@ -282,7 +282,7 @@ bool BreakFalseDeps::runOnMachineFunction(MachineFunction &mf) {
   MF = &mf;
   TII = MF->getSubtarget().getInstrInfo();
   TRI = MF->getSubtarget().getRegisterInfo();
-  RDA = &getAnalysis<ReachingDefAnalysis>();
+  RDI = &getAnalysis<ReachingDefInfoWrapperPass>().getRDI();
 
   RegClassInfo.runOnMachineFunction(mf, /*Rev=*/true);
 

llvm/lib/CodeGen/CodeGen.cpp

@@ -112,6 +112,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
   initializeProcessImplicitDefsLegacyPass(Registry);
   initializeRABasicPass(Registry);
   initializeRAGreedyLegacyPass(Registry);
+  initializeReachingDefInfoWrapperPassPass(Registry);
   initializeRegAllocFastPass(Registry);
   initializeRegUsageInfoCollectorLegacyPass(Registry);
   initializeRegUsageInfoPropagationLegacyPass(Registry);

llvm/lib/CodeGen/ExecutionDomainFix.cpp

@@ -337,9 +337,9 @@ void ExecutionDomainFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
     }
     // Sorted insertion.
     // Enables giving priority to the latest domains during merging.
-    const int Def = RDA->getReachingDef(mi, RC->getRegister(rx));
+    const int Def = RDI->getReachingDef(mi, RC->getRegister(rx));
     auto I = partition_point(Regs, [&](int I) {
-      return RDA->getReachingDef(mi, RC->getRegister(I)) <= Def;
+      return RDI->getReachingDef(mi, RC->getRegister(I)) <= Def;
     });
     Regs.insert(I, rx);
   }
@@ -435,7 +435,7 @@ bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) {
   if (!anyregs)
     return false;
 
-  RDA = &getAnalysis<ReachingDefAnalysis>();
+  RDI = &getAnalysis<ReachingDefInfoWrapperPass>().getRDI();
 
   // Initialize the AliasMap on the first use.
   if (AliasMap.empty()) {