[RISCV][test] Add additional check-prefixes to fix conflicts in tests #160689
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These are all cases where check lines were being silently dropped prior to llvm#159321 which added proper warnings. I did `find llvm/test/CodeGen/RISCV -name "*.ll" -exec ./llvm/utils/update_llc_test_checks.py --llc-bin=./remote-llc -u {} \;` and went through all cases that emitted the new warning.
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@llvm/pr-subscribers-backend-risc-v Author: Alex Bradbury (asb) ChangesThese are all cases where check lines were being silently dropped prior to #159321 which added proper warnings. I did
Patch is 276.72 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/160689.diff 10 Files Affected:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
index 7f387a763b6da..7fb7bdded30f7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
@@ -10,7 +10,7 @@
; RUN: | FileCheck -check-prefix=RV64IF %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -global-isel -mattr=+d \
; RUN: -target-abi=lp64d \
-; RUN: | FileCheck -check-prefix=RV64IF %s
+; RUN: | FileCheck -check-prefix=RV64IF,RV64IFD %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -global-isel \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -global-isel \
@@ -27,6 +27,11 @@ define float @sqrt_f32(float %a) nounwind {
; RV64IF-NEXT: fsqrt.s fa0, fa0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: sqrt_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fsqrt.s fa0, fa0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: sqrt_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -68,6 +73,16 @@ define float @powi_f32(float %a, i32 %b) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: powi_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: sext.w a0, a0
+; RV64IFD-NEXT: call __powisf2
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: powi_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -109,6 +124,15 @@ define float @sin_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: sin_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call sinf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: sin_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -149,6 +173,15 @@ define float @cos_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: cos_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call cosf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: cos_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -190,6 +223,42 @@ define float @sincos_f32(float %a) nounwind {
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
;
+; RV64IF-LABEL: sincos_f32:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV64IF-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill
+; RV64IF-NEXT: fmv.s fs0, fa0
+; RV64IF-NEXT: call sinf
+; RV64IF-NEXT: fmv.s fs1, fa0
+; RV64IF-NEXT: fmv.s fa0, fs0
+; RV64IF-NEXT: call cosf
+; RV64IF-NEXT: fadd.s fa0, fs1, fa0
+; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
+; RV64IF-NEXT: flw fs1, 0(sp) # 4-byte Folded Reload
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+;
+; RV64IFD-LABEL: sincos_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -32
+; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: fmv.s fs0, fa0
+; RV64IFD-NEXT: call sinf
+; RV64IFD-NEXT: fmv.s fs1, fa0
+; RV64IFD-NEXT: fmv.s fa0, fs0
+; RV64IFD-NEXT: call cosf
+; RV64IFD-NEXT: fadd.s fa0, fs1, fa0
+; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 32
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: sincos_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -254,6 +323,15 @@ define float @pow_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: pow_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call powf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: pow_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -294,6 +372,15 @@ define float @exp_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: exp_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call expf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: exp_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -334,6 +421,15 @@ define float @exp2_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: exp2_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call exp2f
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: exp2_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -374,6 +470,15 @@ define float @exp10_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: exp10_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call exp10f
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: exp10_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -414,6 +519,15 @@ define float @log_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: log_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call logf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: log_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -454,6 +568,15 @@ define float @log10_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: log10_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call log10f
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: log10_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -494,6 +617,15 @@ define float @log2_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: log2_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call log2f
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: log2_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -526,6 +658,11 @@ define float @fma_f32(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: fma_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fmadd.s fa0, fa0, fa1, fa2
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: fma_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -558,6 +695,11 @@ define float @fmuladd_f32(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: fmuladd_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fmadd.s fa0, fa0, fa1, fa2
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: fmuladd_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -600,6 +742,11 @@ define float @fabs_f32(float %a) nounwind {
; RV64IF-NEXT: fabs.s fa0, fa0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: fabs_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fabs.s fa0, fa0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: fabs_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 1
@@ -626,6 +773,11 @@ define float @minnum_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: fmin.s fa0, fa0, fa1
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: minnum_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fmin.s fa0, fa0, fa1
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: minnum_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -658,6 +810,11 @@ define float @maxnum_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: fmax.s fa0, fa0, fa1
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: maxnum_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fmax.s fa0, fa0, fa1
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: maxnum_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -690,6 +847,11 @@ define float @copysign_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: fsgnj.s fa0, fa0, fa1
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: copysign_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fsgnj.s fa0, fa0, fa1
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: copysign_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
@@ -730,6 +892,15 @@ define float @ceil_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: ceil_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call ceilf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: ceil_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -770,6 +941,15 @@ define float @trunc_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: trunc_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call truncf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: trunc_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -810,6 +990,15 @@ define float @rint_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: rint_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call rintf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: rint_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -850,6 +1039,15 @@ define float @nearbyint_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: nearbyint_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call nearbyintf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: nearbyint_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -890,6 +1088,15 @@ define float @round_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: round_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call roundf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: round_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -930,6 +1137,15 @@ define float @roundeven_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: roundeven_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call roundevenf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: roundeven_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -966,6 +1182,13 @@ define i1 @fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 927
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1039,6 +1262,13 @@ define i1 @isnan_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isnan_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 768
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isnan_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1073,6 +1303,13 @@ define i1 @isqnan_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isqnan_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 512
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isqnan_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 1
@@ -1109,6 +1346,13 @@ define i1 @issnan_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: issnan_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 256
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: issnan_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1149,6 +1393,13 @@ define i1 @isinf_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isinf_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 129
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isinf_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1185,6 +1436,13 @@ define i1 @isposinf_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isposinf_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 128
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isposinf_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1218,6 +1476,13 @@ define i1 @isneginf_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isneginf_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 1
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isneginf_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1046528
@@ -1251,6 +1516,13 @@ define i1 @isfinite_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isfinite_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 126
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isfinite_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1285,6 +1557,13 @@ define i1 @isposfinite_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isposfinite_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 112
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isposfinite_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1316,6 +1595,13 @@ define i1 @isnegfinite_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isnegfinite_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 14
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isnegfinite_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1357,6 +1643,13 @@ define i1 @isnotfinite_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isnotfinite_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 897
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isnotfinite_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1401,6 +1694,15 @@ define float @tan_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: tan_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call tanf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: tan_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1442,6 +1744,16 @@ define float @ldexp_float(float %x, i32 %y) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: ldexp_float:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: sext.w a0, a0
+; RV64IFD-NEXT: call ldexpf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: ldexp_float:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1483,6 +1795,15 @@ define float @asin_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: asin_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call asinf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: asin_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1523,6 +1844,15 @@ define float @acos_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: acos_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call acosf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: acos_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1563,6 +1893,15 @@ define float @atan_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: atan_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call atanf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: atan_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1603,6 +1942,15 @@ define float @atan2_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: atan2_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call atan2f
+; RV64IFD-NEXT: ld ra, ...
[truncated]
|
|
@llvm/pr-subscribers-llvm-globalisel Author: Alex Bradbury (asb) ChangesThese are all cases where check lines were being silently dropped prior to #159321 which added proper warnings. I did
Patch is 276.72 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/160689.diff 10 Files Affected:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
index 7f387a763b6da..7fb7bdded30f7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
@@ -10,7 +10,7 @@
; RUN: | FileCheck -check-prefix=RV64IF %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -global-isel -mattr=+d \
; RUN: -target-abi=lp64d \
-; RUN: | FileCheck -check-prefix=RV64IF %s
+; RUN: | FileCheck -check-prefix=RV64IF,RV64IFD %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -global-isel \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -global-isel \
@@ -27,6 +27,11 @@ define float @sqrt_f32(float %a) nounwind {
; RV64IF-NEXT: fsqrt.s fa0, fa0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: sqrt_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fsqrt.s fa0, fa0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: sqrt_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -68,6 +73,16 @@ define float @powi_f32(float %a, i32 %b) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: powi_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: sext.w a0, a0
+; RV64IFD-NEXT: call __powisf2
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: powi_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -109,6 +124,15 @@ define float @sin_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: sin_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call sinf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: sin_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -149,6 +173,15 @@ define float @cos_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: cos_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call cosf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: cos_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -190,6 +223,42 @@ define float @sincos_f32(float %a) nounwind {
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
;
+; RV64IF-LABEL: sincos_f32:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV64IF-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill
+; RV64IF-NEXT: fmv.s fs0, fa0
+; RV64IF-NEXT: call sinf
+; RV64IF-NEXT: fmv.s fs1, fa0
+; RV64IF-NEXT: fmv.s fa0, fs0
+; RV64IF-NEXT: call cosf
+; RV64IF-NEXT: fadd.s fa0, fs1, fa0
+; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
+; RV64IF-NEXT: flw fs1, 0(sp) # 4-byte Folded Reload
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+;
+; RV64IFD-LABEL: sincos_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -32
+; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: fmv.s fs0, fa0
+; RV64IFD-NEXT: call sinf
+; RV64IFD-NEXT: fmv.s fs1, fa0
+; RV64IFD-NEXT: fmv.s fa0, fs0
+; RV64IFD-NEXT: call cosf
+; RV64IFD-NEXT: fadd.s fa0, fs1, fa0
+; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 32
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: sincos_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -254,6 +323,15 @@ define float @pow_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: pow_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call powf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: pow_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -294,6 +372,15 @@ define float @exp_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: exp_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call expf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: exp_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -334,6 +421,15 @@ define float @exp2_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: exp2_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call exp2f
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: exp2_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -374,6 +470,15 @@ define float @exp10_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: exp10_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call exp10f
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: exp10_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -414,6 +519,15 @@ define float @log_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: log_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call logf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: log_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -454,6 +568,15 @@ define float @log10_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: log10_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call log10f
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: log10_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -494,6 +617,15 @@ define float @log2_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: log2_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call log2f
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: log2_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -526,6 +658,11 @@ define float @fma_f32(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: fma_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fmadd.s fa0, fa0, fa1, fa2
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: fma_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -558,6 +695,11 @@ define float @fmuladd_f32(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: fmuladd_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fmadd.s fa0, fa0, fa1, fa2
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: fmuladd_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -600,6 +742,11 @@ define float @fabs_f32(float %a) nounwind {
; RV64IF-NEXT: fabs.s fa0, fa0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: fabs_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fabs.s fa0, fa0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: fabs_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 1
@@ -626,6 +773,11 @@ define float @minnum_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: fmin.s fa0, fa0, fa1
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: minnum_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fmin.s fa0, fa0, fa1
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: minnum_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -658,6 +810,11 @@ define float @maxnum_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: fmax.s fa0, fa0, fa1
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: maxnum_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fmax.s fa0, fa0, fa1
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: maxnum_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -690,6 +847,11 @@ define float @copysign_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: fsgnj.s fa0, fa0, fa1
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: copysign_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fsgnj.s fa0, fa0, fa1
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: copysign_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
@@ -730,6 +892,15 @@ define float @ceil_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: ceil_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call ceilf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: ceil_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -770,6 +941,15 @@ define float @trunc_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: trunc_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call truncf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: trunc_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -810,6 +990,15 @@ define float @rint_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: rint_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call rintf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: rint_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -850,6 +1039,15 @@ define float @nearbyint_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: nearbyint_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call nearbyintf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: nearbyint_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -890,6 +1088,15 @@ define float @round_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: round_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call roundf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: round_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -930,6 +1137,15 @@ define float @roundeven_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: roundeven_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call roundevenf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: roundeven_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -966,6 +1182,13 @@ define i1 @fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 927
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1039,6 +1262,13 @@ define i1 @isnan_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isnan_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 768
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isnan_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1073,6 +1303,13 @@ define i1 @isqnan_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isqnan_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 512
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isqnan_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 1
@@ -1109,6 +1346,13 @@ define i1 @issnan_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: issnan_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 256
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: issnan_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1149,6 +1393,13 @@ define i1 @isinf_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isinf_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 129
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isinf_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1185,6 +1436,13 @@ define i1 @isposinf_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isposinf_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 128
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isposinf_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1218,6 +1476,13 @@ define i1 @isneginf_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isneginf_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 1
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isneginf_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1046528
@@ -1251,6 +1516,13 @@ define i1 @isfinite_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isfinite_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 126
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isfinite_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1285,6 +1557,13 @@ define i1 @isposfinite_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isposfinite_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 112
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isposfinite_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1316,6 +1595,13 @@ define i1 @isnegfinite_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isnegfinite_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 14
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isnegfinite_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1357,6 +1643,13 @@ define i1 @isnotfinite_fpclass(float %x) {
; RV64IF-NEXT: snez a0, a0
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: isnotfinite_fpclass:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: fclass.s a0, fa0
+; RV64IFD-NEXT: andi a0, a0, 897
+; RV64IFD-NEXT: snez a0, a0
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: isnotfinite_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 522240
@@ -1401,6 +1694,15 @@ define float @tan_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: tan_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call tanf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: tan_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1442,6 +1744,16 @@ define float @ldexp_float(float %x, i32 %y) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: ldexp_float:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: sext.w a0, a0
+; RV64IFD-NEXT: call ldexpf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: ldexp_float:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1483,6 +1795,15 @@ define float @asin_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: asin_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call asinf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: asin_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1523,6 +1844,15 @@ define float @acos_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: acos_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call acosf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: acos_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1563,6 +1893,15 @@ define float @atan_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: atan_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call atanf
+; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT: addi sp, sp, 16
+; RV64IFD-NEXT: ret
+;
; RV32I-LABEL: atan_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -1603,6 +1942,15 @@ define float @atan2_f32(float %a, float %b) nounwind {
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
;
+; RV64IFD-LABEL: atan2_f32:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addi sp, sp, -16
+; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT: call atan2f
+; RV64IFD-NEXT: ld ra, ...
[truncated]
|
lukel97
approved these changes
Sep 25, 2025
| ; Check that the default value enables the web folding and | ||
| ; that it is bigger than 3. | ||
| ; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+f,+d -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=FOLDING | ||
| ; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+f,+d -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=FOLDING,ZVFH |
There was a problem hiding this comment.
Just checking there's no difference in the output between this run line and the --riscv-lower-ext-max-web-size=3 version above?
mahesh-attarde
pushed a commit
to mahesh-attarde/llvm-project
that referenced
this pull request
Oct 3, 2025
…llvm#160689) These are all cases where check lines were being silently dropped prior to llvm#159321 which added proper warnings. I did `find llvm/test/CodeGen/RISCV -name "*.ll" -exec ./llvm/utils/update_llc_test_checks.py --llc-bin=./remote-llc -u {} \;` and went through all cases that emitted the new warning. `idiv_large.ll` is a case that seems to not be generated by update_llc_test_checks but still has the comment indicating it was (presumably it was hand-edited after generation).
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These are all cases where check lines were being silently dropped prior to #159321 which added proper warnings.
I did
find llvm/test/CodeGen/RISCV -name "*.ll" -exec ./llvm/utils/update_llc_test_checks.py --llc-bin=./remote-llc -u {} \;and went through all cases that emitted the new warning.idiv_large.llis a case that seems to not be generated by update_llc_test_checks but still has the comment indicating it was (presumably it was hand-edited after generation).