[NFC][LLVM] Pass/return SMLoc by value instead of const reference #160797
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SMLoc itself encapsulates just a pointer, so there is no need to pass or return it by reference.
llvmbot
added
backend:ARM
backend:AMDGPU
backend:X86
llvm:mc
|
@llvm/pr-subscribers-llvm-support @llvm/pr-subscribers-testing-tools Author: Rahul Joshi (jurahul) ChangesSMLoc itself encapsulates just a pointer, so there is no need to pass or return it by reference. Full diff: https://github.com/llvm/llvm-project/pull/160797.diff 8 Files Affected:
diff --git a/llvm/include/llvm/Support/SMLoc.h b/llvm/include/llvm/Support/SMLoc.h
index d7dde81ce0be7..c80969b1d83dc 100644
--- a/llvm/include/llvm/Support/SMLoc.h
+++ b/llvm/include/llvm/Support/SMLoc.h
@@ -28,8 +28,8 @@ class SMLoc {
constexpr bool isValid() const { return Ptr != nullptr; }
- constexpr bool operator==(const SMLoc &RHS) const { return RHS.Ptr == Ptr; }
- constexpr bool operator!=(const SMLoc &RHS) const { return RHS.Ptr != Ptr; }
+ constexpr bool operator==(SMLoc RHS) const { return RHS.Ptr == Ptr; }
+ constexpr bool operator!=(SMLoc RHS) const { return RHS.Ptr != Ptr; }
constexpr const char *getPointer() const { return Ptr; }
diff --git a/llvm/include/llvm/TableGen/Record.h b/llvm/include/llvm/TableGen/Record.h
index d4fa1e5d65749..cb2721aba4f25 100644
--- a/llvm/include/llvm/TableGen/Record.h
+++ b/llvm/include/llvm/TableGen/Record.h
@@ -1577,7 +1577,7 @@ class RecordVal {
}
/// Get the source location of the point where the field was defined.
- const SMLoc &getLoc() const { return Loc; }
+ SMLoc getLoc() const { return Loc; }
/// Is this a field where nonconcrete values are okay?
bool isNonconcreteOK() const {
diff --git a/llvm/lib/MC/MCSFrame.cpp b/llvm/lib/MC/MCSFrame.cpp
index 910fcab7b4d75..d6fa54c087ca3 100644
--- a/llvm/lib/MC/MCSFrame.cpp
+++ b/llvm/lib/MC/MCSFrame.cpp
@@ -200,7 +200,7 @@ class SFrameEmitterImpl {
return false;
}
- bool setCFAOffset(SFrameFRE &FRE, const SMLoc &Loc, size_t Offset) {
+ bool setCFAOffset(SFrameFRE &FRE, SMLoc Loc, size_t Offset) {
if (!FRE.CFARegSet) {
Streamer.getContext().reportWarning(
Loc, "adjusting CFA offset without a base register. "
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index dfbde85231a6e..a67a7bedf19a3 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1807,7 +1807,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
const OperandVector &Operands) const;
SMLoc getInstLoc(const OperandVector &Operands) const;
- bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
+ bool validateInstruction(const MCInst &Inst, SMLoc IDLoc,
+ const OperandVector &Operands);
bool validateOffset(const MCInst &Inst, const OperandVector &Operands);
bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
@@ -1824,8 +1825,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateMIMGAtomicDMask(const MCInst &Inst);
bool validateMIMGGatherDMask(const MCInst &Inst);
bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);
- bool validateMIMGDataSize(const MCInst &Inst, const SMLoc &IDLoc);
- bool validateMIMGAddrSize(const MCInst &Inst, const SMLoc &IDLoc);
+ bool validateMIMGDataSize(const MCInst &Inst, SMLoc IDLoc);
+ bool validateMIMGAddrSize(const MCInst &Inst, SMLoc IDLoc);
bool validateMIMGD16(const MCInst &Inst);
bool validateMIMGDim(const MCInst &Inst, const OperandVector &Operands);
bool validateTensorR128(const MCInst &Inst);
@@ -1847,7 +1848,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateDivScale(const MCInst &Inst);
bool validateWaitCnt(const MCInst &Inst, const OperandVector &Operands);
bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
- const SMLoc &IDLoc);
+ SMLoc IDLoc);
bool validateTHAndScopeBits(const MCInst &Inst, const OperandVector &Operands,
const unsigned CPol);
bool validateTFE(const MCInst &Inst, const OperandVector &Operands);
@@ -1864,7 +1865,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool isSupportedMnemo(StringRef Mnemo,
const FeatureBitset &FBS,
ArrayRef<unsigned> Variants);
- bool checkUnsupportedInstruction(StringRef Name, const SMLoc &IDLoc);
+ bool checkUnsupportedInstruction(StringRef Name, SMLoc IDLoc);
bool isId(const StringRef Id) const;
bool isId(const AsmToken &Token, const StringRef Id) const;
@@ -4087,8 +4088,7 @@ bool AMDGPUAsmParser::validateIntClampSupported(const MCInst &Inst) {
constexpr uint64_t MIMGFlags =
SIInstrFlags::MIMG | SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE;
-bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,
- const SMLoc &IDLoc) {
+bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst, SMLoc IDLoc) {
const unsigned Opc = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opc);
@@ -4135,8 +4135,7 @@ bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,
return false;
}
-bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
- const SMLoc &IDLoc) {
+bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst, SMLoc IDLoc) {
const unsigned Opc = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opc);
@@ -5344,7 +5343,7 @@ bool AMDGPUAsmParser::validateGWS(const MCInst &Inst,
bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
const OperandVector &Operands,
- const SMLoc &IDLoc) {
+ SMLoc IDLoc) {
int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
AMDGPU::OpName::cpol);
if (CPolPos == -1)
@@ -5541,8 +5540,7 @@ bool AMDGPUAsmParser::validateWMMA(const MCInst &Inst,
validateFmt(AMDGPU::OpName::matrix_b_fmt, AMDGPU::OpName::src1);
}
-bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
- const SMLoc &IDLoc,
+bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst, SMLoc IDLoc,
const OperandVector &Operands) {
if (!validateLdsDirect(Inst, Operands))
return false;
@@ -5704,7 +5702,7 @@ bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,
}
bool AMDGPUAsmParser::checkUnsupportedInstruction(StringRef Mnemo,
- const SMLoc &IDLoc) {
+ SMLoc IDLoc) {
FeatureBitset FBS = ComputeAvailableFeatures(getFeatureBits());
// Check if requested instruction variant is supported.
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 0e974838a7c6b..f60660b12baca 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -135,17 +135,17 @@ class UnwindContext {
MCRegister getFPReg() const { return FPReg; }
void emitFnStartLocNotes() const {
- for (const SMLoc &Loc : FnStartLocs)
+ for (SMLoc Loc : FnStartLocs)
Parser.Note(Loc, ".fnstart was specified here");
}
void emitCantUnwindLocNotes() const {
- for (const SMLoc &Loc : CantUnwindLocs)
+ for (SMLoc Loc : CantUnwindLocs)
Parser.Note(Loc, ".cantunwind was specified here");
}
void emitHandlerDataLocNotes() const {
- for (const SMLoc &Loc : HandlerDataLocs)
+ for (SMLoc Loc : HandlerDataLocs)
Parser.Note(Loc, ".handlerdata was specified here");
}
diff --git a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
index 3e9666f586e0f..deef39407ea35 100644
--- a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
+++ b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
@@ -39,9 +39,9 @@ class M68kAsmParser : public MCTargetAsmParser {
#include "M68kGenAsmMatcher.inc"
// Helpers for Match&Emit.
- bool invalidOperand(const SMLoc &Loc, const OperandVector &Operands,
+ bool invalidOperand(SMLoc Loc, const OperandVector &Operands,
const uint64_t &ErrorInfo);
- bool missingFeature(const SMLoc &Loc, const uint64_t &ErrorInfo);
+ bool missingFeature(SMLoc Loc, const uint64_t &ErrorInfo);
bool emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const;
bool parseRegisterName(MCRegister &RegNo, SMLoc Loc, StringRef RegisterName);
ParseStatus parseRegister(MCRegister &RegNo);
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 253b737ce2290..a8908d4b710e6 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1247,7 +1247,7 @@ class X86AsmParser : public MCTargetAsmParser {
/// return false if no parsing errors occurred, true otherwise.
bool HandleAVX512Operand(OperandVector &Operands);
- bool ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc);
+ bool ParseZ(std::unique_ptr<X86Operand> &Z, SMLoc StartLoc);
bool is64BitMode() const {
// FIXME: Can tablegen auto-generate this?
@@ -2907,8 +2907,7 @@ X86::CondCode X86AsmParser::ParseConditionCode(StringRef CC) {
// true on failure, false otherwise
// If no {z} mark was found - Parser doesn't advance
-bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z,
- const SMLoc &StartLoc) {
+bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z, SMLoc StartLoc) {
MCAsmParser &Parser = getParser();
// Assuming we are just pass the '{' mark, quering the next token
// Searched for {z}, but none was found. Return false, as no parsing error was
diff --git a/llvm/utils/FileCheck/FileCheck.cpp b/llvm/utils/FileCheck/FileCheck.cpp
index 185b6b30994fc..305c28b4c7257 100644
--- a/llvm/utils/FileCheck/FileCheck.cpp
+++ b/llvm/utils/FileCheck/FileCheck.cpp
@@ -384,7 +384,7 @@ BuildInputAnnotations(const SourceMgr &SM, unsigned CheckFileBufferID,
std::vector<InputAnnotation> &Annotations,
unsigned &LabelWidth) {
struct CompareSMLoc {
- bool operator()(const SMLoc &LHS, const SMLoc &RHS) const {
+ bool operator()(SMLoc LHS, SMLoc RHS) const {
return LHS.getPointer() < RHS.getPointer();
}
};
|
|
@llvm/pr-subscribers-llvm-mc Author: Rahul Joshi (jurahul) ChangesSMLoc itself encapsulates just a pointer, so there is no need to pass or return it by reference. Full diff: https://github.com/llvm/llvm-project/pull/160797.diff 8 Files Affected:
diff --git a/llvm/include/llvm/Support/SMLoc.h b/llvm/include/llvm/Support/SMLoc.h
index d7dde81ce0be7..c80969b1d83dc 100644
--- a/llvm/include/llvm/Support/SMLoc.h
+++ b/llvm/include/llvm/Support/SMLoc.h
@@ -28,8 +28,8 @@ class SMLoc {
constexpr bool isValid() const { return Ptr != nullptr; }
- constexpr bool operator==(const SMLoc &RHS) const { return RHS.Ptr == Ptr; }
- constexpr bool operator!=(const SMLoc &RHS) const { return RHS.Ptr != Ptr; }
+ constexpr bool operator==(SMLoc RHS) const { return RHS.Ptr == Ptr; }
+ constexpr bool operator!=(SMLoc RHS) const { return RHS.Ptr != Ptr; }
constexpr const char *getPointer() const { return Ptr; }
diff --git a/llvm/include/llvm/TableGen/Record.h b/llvm/include/llvm/TableGen/Record.h
index d4fa1e5d65749..cb2721aba4f25 100644
--- a/llvm/include/llvm/TableGen/Record.h
+++ b/llvm/include/llvm/TableGen/Record.h
@@ -1577,7 +1577,7 @@ class RecordVal {
}
/// Get the source location of the point where the field was defined.
- const SMLoc &getLoc() const { return Loc; }
+ SMLoc getLoc() const { return Loc; }
/// Is this a field where nonconcrete values are okay?
bool isNonconcreteOK() const {
diff --git a/llvm/lib/MC/MCSFrame.cpp b/llvm/lib/MC/MCSFrame.cpp
index 910fcab7b4d75..d6fa54c087ca3 100644
--- a/llvm/lib/MC/MCSFrame.cpp
+++ b/llvm/lib/MC/MCSFrame.cpp
@@ -200,7 +200,7 @@ class SFrameEmitterImpl {
return false;
}
- bool setCFAOffset(SFrameFRE &FRE, const SMLoc &Loc, size_t Offset) {
+ bool setCFAOffset(SFrameFRE &FRE, SMLoc Loc, size_t Offset) {
if (!FRE.CFARegSet) {
Streamer.getContext().reportWarning(
Loc, "adjusting CFA offset without a base register. "
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index dfbde85231a6e..a67a7bedf19a3 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1807,7 +1807,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
const OperandVector &Operands) const;
SMLoc getInstLoc(const OperandVector &Operands) const;
- bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
+ bool validateInstruction(const MCInst &Inst, SMLoc IDLoc,
+ const OperandVector &Operands);
bool validateOffset(const MCInst &Inst, const OperandVector &Operands);
bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
@@ -1824,8 +1825,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateMIMGAtomicDMask(const MCInst &Inst);
bool validateMIMGGatherDMask(const MCInst &Inst);
bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);
- bool validateMIMGDataSize(const MCInst &Inst, const SMLoc &IDLoc);
- bool validateMIMGAddrSize(const MCInst &Inst, const SMLoc &IDLoc);
+ bool validateMIMGDataSize(const MCInst &Inst, SMLoc IDLoc);
+ bool validateMIMGAddrSize(const MCInst &Inst, SMLoc IDLoc);
bool validateMIMGD16(const MCInst &Inst);
bool validateMIMGDim(const MCInst &Inst, const OperandVector &Operands);
bool validateTensorR128(const MCInst &Inst);
@@ -1847,7 +1848,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateDivScale(const MCInst &Inst);
bool validateWaitCnt(const MCInst &Inst, const OperandVector &Operands);
bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
- const SMLoc &IDLoc);
+ SMLoc IDLoc);
bool validateTHAndScopeBits(const MCInst &Inst, const OperandVector &Operands,
const unsigned CPol);
bool validateTFE(const MCInst &Inst, const OperandVector &Operands);
@@ -1864,7 +1865,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool isSupportedMnemo(StringRef Mnemo,
const FeatureBitset &FBS,
ArrayRef<unsigned> Variants);
- bool checkUnsupportedInstruction(StringRef Name, const SMLoc &IDLoc);
+ bool checkUnsupportedInstruction(StringRef Name, SMLoc IDLoc);
bool isId(const StringRef Id) const;
bool isId(const AsmToken &Token, const StringRef Id) const;
@@ -4087,8 +4088,7 @@ bool AMDGPUAsmParser::validateIntClampSupported(const MCInst &Inst) {
constexpr uint64_t MIMGFlags =
SIInstrFlags::MIMG | SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE;
-bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,
- const SMLoc &IDLoc) {
+bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst, SMLoc IDLoc) {
const unsigned Opc = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opc);
@@ -4135,8 +4135,7 @@ bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,
return false;
}
-bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
- const SMLoc &IDLoc) {
+bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst, SMLoc IDLoc) {
const unsigned Opc = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opc);
@@ -5344,7 +5343,7 @@ bool AMDGPUAsmParser::validateGWS(const MCInst &Inst,
bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
const OperandVector &Operands,
- const SMLoc &IDLoc) {
+ SMLoc IDLoc) {
int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
AMDGPU::OpName::cpol);
if (CPolPos == -1)
@@ -5541,8 +5540,7 @@ bool AMDGPUAsmParser::validateWMMA(const MCInst &Inst,
validateFmt(AMDGPU::OpName::matrix_b_fmt, AMDGPU::OpName::src1);
}
-bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
- const SMLoc &IDLoc,
+bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst, SMLoc IDLoc,
const OperandVector &Operands) {
if (!validateLdsDirect(Inst, Operands))
return false;
@@ -5704,7 +5702,7 @@ bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,
}
bool AMDGPUAsmParser::checkUnsupportedInstruction(StringRef Mnemo,
- const SMLoc &IDLoc) {
+ SMLoc IDLoc) {
FeatureBitset FBS = ComputeAvailableFeatures(getFeatureBits());
// Check if requested instruction variant is supported.
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 0e974838a7c6b..f60660b12baca 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -135,17 +135,17 @@ class UnwindContext {
MCRegister getFPReg() const { return FPReg; }
void emitFnStartLocNotes() const {
- for (const SMLoc &Loc : FnStartLocs)
+ for (SMLoc Loc : FnStartLocs)
Parser.Note(Loc, ".fnstart was specified here");
}
void emitCantUnwindLocNotes() const {
- for (const SMLoc &Loc : CantUnwindLocs)
+ for (SMLoc Loc : CantUnwindLocs)
Parser.Note(Loc, ".cantunwind was specified here");
}
void emitHandlerDataLocNotes() const {
- for (const SMLoc &Loc : HandlerDataLocs)
+ for (SMLoc Loc : HandlerDataLocs)
Parser.Note(Loc, ".handlerdata was specified here");
}
diff --git a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
index 3e9666f586e0f..deef39407ea35 100644
--- a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
+++ b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
@@ -39,9 +39,9 @@ class M68kAsmParser : public MCTargetAsmParser {
#include "M68kGenAsmMatcher.inc"
// Helpers for Match&Emit.
- bool invalidOperand(const SMLoc &Loc, const OperandVector &Operands,
+ bool invalidOperand(SMLoc Loc, const OperandVector &Operands,
const uint64_t &ErrorInfo);
- bool missingFeature(const SMLoc &Loc, const uint64_t &ErrorInfo);
+ bool missingFeature(SMLoc Loc, const uint64_t &ErrorInfo);
bool emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const;
bool parseRegisterName(MCRegister &RegNo, SMLoc Loc, StringRef RegisterName);
ParseStatus parseRegister(MCRegister &RegNo);
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 253b737ce2290..a8908d4b710e6 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1247,7 +1247,7 @@ class X86AsmParser : public MCTargetAsmParser {
/// return false if no parsing errors occurred, true otherwise.
bool HandleAVX512Operand(OperandVector &Operands);
- bool ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc);
+ bool ParseZ(std::unique_ptr<X86Operand> &Z, SMLoc StartLoc);
bool is64BitMode() const {
// FIXME: Can tablegen auto-generate this?
@@ -2907,8 +2907,7 @@ X86::CondCode X86AsmParser::ParseConditionCode(StringRef CC) {
// true on failure, false otherwise
// If no {z} mark was found - Parser doesn't advance
-bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z,
- const SMLoc &StartLoc) {
+bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z, SMLoc StartLoc) {
MCAsmParser &Parser = getParser();
// Assuming we are just pass the '{' mark, quering the next token
// Searched for {z}, but none was found. Return false, as no parsing error was
diff --git a/llvm/utils/FileCheck/FileCheck.cpp b/llvm/utils/FileCheck/FileCheck.cpp
index 185b6b30994fc..305c28b4c7257 100644
--- a/llvm/utils/FileCheck/FileCheck.cpp
+++ b/llvm/utils/FileCheck/FileCheck.cpp
@@ -384,7 +384,7 @@ BuildInputAnnotations(const SourceMgr &SM, unsigned CheckFileBufferID,
std::vector<InputAnnotation> &Annotations,
unsigned &LabelWidth) {
struct CompareSMLoc {
- bool operator()(const SMLoc &LHS, const SMLoc &RHS) const {
+ bool operator()(SMLoc LHS, SMLoc RHS) const {
return LHS.getPointer() < RHS.getPointer();
}
};
|
|
@llvm/pr-subscribers-backend-amdgpu Author: Rahul Joshi (jurahul) ChangesSMLoc itself encapsulates just a pointer, so there is no need to pass or return it by reference. Full diff: https://github.com/llvm/llvm-project/pull/160797.diff 8 Files Affected:
diff --git a/llvm/include/llvm/Support/SMLoc.h b/llvm/include/llvm/Support/SMLoc.h
index d7dde81ce0be7..c80969b1d83dc 100644
--- a/llvm/include/llvm/Support/SMLoc.h
+++ b/llvm/include/llvm/Support/SMLoc.h
@@ -28,8 +28,8 @@ class SMLoc {
constexpr bool isValid() const { return Ptr != nullptr; }
- constexpr bool operator==(const SMLoc &RHS) const { return RHS.Ptr == Ptr; }
- constexpr bool operator!=(const SMLoc &RHS) const { return RHS.Ptr != Ptr; }
+ constexpr bool operator==(SMLoc RHS) const { return RHS.Ptr == Ptr; }
+ constexpr bool operator!=(SMLoc RHS) const { return RHS.Ptr != Ptr; }
constexpr const char *getPointer() const { return Ptr; }
diff --git a/llvm/include/llvm/TableGen/Record.h b/llvm/include/llvm/TableGen/Record.h
index d4fa1e5d65749..cb2721aba4f25 100644
--- a/llvm/include/llvm/TableGen/Record.h
+++ b/llvm/include/llvm/TableGen/Record.h
@@ -1577,7 +1577,7 @@ class RecordVal {
}
/// Get the source location of the point where the field was defined.
- const SMLoc &getLoc() const { return Loc; }
+ SMLoc getLoc() const { return Loc; }
/// Is this a field where nonconcrete values are okay?
bool isNonconcreteOK() const {
diff --git a/llvm/lib/MC/MCSFrame.cpp b/llvm/lib/MC/MCSFrame.cpp
index 910fcab7b4d75..d6fa54c087ca3 100644
--- a/llvm/lib/MC/MCSFrame.cpp
+++ b/llvm/lib/MC/MCSFrame.cpp
@@ -200,7 +200,7 @@ class SFrameEmitterImpl {
return false;
}
- bool setCFAOffset(SFrameFRE &FRE, const SMLoc &Loc, size_t Offset) {
+ bool setCFAOffset(SFrameFRE &FRE, SMLoc Loc, size_t Offset) {
if (!FRE.CFARegSet) {
Streamer.getContext().reportWarning(
Loc, "adjusting CFA offset without a base register. "
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index dfbde85231a6e..a67a7bedf19a3 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1807,7 +1807,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
const OperandVector &Operands) const;
SMLoc getInstLoc(const OperandVector &Operands) const;
- bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
+ bool validateInstruction(const MCInst &Inst, SMLoc IDLoc,
+ const OperandVector &Operands);
bool validateOffset(const MCInst &Inst, const OperandVector &Operands);
bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
@@ -1824,8 +1825,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateMIMGAtomicDMask(const MCInst &Inst);
bool validateMIMGGatherDMask(const MCInst &Inst);
bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);
- bool validateMIMGDataSize(const MCInst &Inst, const SMLoc &IDLoc);
- bool validateMIMGAddrSize(const MCInst &Inst, const SMLoc &IDLoc);
+ bool validateMIMGDataSize(const MCInst &Inst, SMLoc IDLoc);
+ bool validateMIMGAddrSize(const MCInst &Inst, SMLoc IDLoc);
bool validateMIMGD16(const MCInst &Inst);
bool validateMIMGDim(const MCInst &Inst, const OperandVector &Operands);
bool validateTensorR128(const MCInst &Inst);
@@ -1847,7 +1848,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateDivScale(const MCInst &Inst);
bool validateWaitCnt(const MCInst &Inst, const OperandVector &Operands);
bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
- const SMLoc &IDLoc);
+ SMLoc IDLoc);
bool validateTHAndScopeBits(const MCInst &Inst, const OperandVector &Operands,
const unsigned CPol);
bool validateTFE(const MCInst &Inst, const OperandVector &Operands);
@@ -1864,7 +1865,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool isSupportedMnemo(StringRef Mnemo,
const FeatureBitset &FBS,
ArrayRef<unsigned> Variants);
- bool checkUnsupportedInstruction(StringRef Name, const SMLoc &IDLoc);
+ bool checkUnsupportedInstruction(StringRef Name, SMLoc IDLoc);
bool isId(const StringRef Id) const;
bool isId(const AsmToken &Token, const StringRef Id) const;
@@ -4087,8 +4088,7 @@ bool AMDGPUAsmParser::validateIntClampSupported(const MCInst &Inst) {
constexpr uint64_t MIMGFlags =
SIInstrFlags::MIMG | SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE;
-bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,
- const SMLoc &IDLoc) {
+bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst, SMLoc IDLoc) {
const unsigned Opc = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opc);
@@ -4135,8 +4135,7 @@ bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,
return false;
}
-bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
- const SMLoc &IDLoc) {
+bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst, SMLoc IDLoc) {
const unsigned Opc = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opc);
@@ -5344,7 +5343,7 @@ bool AMDGPUAsmParser::validateGWS(const MCInst &Inst,
bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
const OperandVector &Operands,
- const SMLoc &IDLoc) {
+ SMLoc IDLoc) {
int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
AMDGPU::OpName::cpol);
if (CPolPos == -1)
@@ -5541,8 +5540,7 @@ bool AMDGPUAsmParser::validateWMMA(const MCInst &Inst,
validateFmt(AMDGPU::OpName::matrix_b_fmt, AMDGPU::OpName::src1);
}
-bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
- const SMLoc &IDLoc,
+bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst, SMLoc IDLoc,
const OperandVector &Operands) {
if (!validateLdsDirect(Inst, Operands))
return false;
@@ -5704,7 +5702,7 @@ bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,
}
bool AMDGPUAsmParser::checkUnsupportedInstruction(StringRef Mnemo,
- const SMLoc &IDLoc) {
+ SMLoc IDLoc) {
FeatureBitset FBS = ComputeAvailableFeatures(getFeatureBits());
// Check if requested instruction variant is supported.
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 0e974838a7c6b..f60660b12baca 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -135,17 +135,17 @@ class UnwindContext {
MCRegister getFPReg() const { return FPReg; }
void emitFnStartLocNotes() const {
- for (const SMLoc &Loc : FnStartLocs)
+ for (SMLoc Loc : FnStartLocs)
Parser.Note(Loc, ".fnstart was specified here");
}
void emitCantUnwindLocNotes() const {
- for (const SMLoc &Loc : CantUnwindLocs)
+ for (SMLoc Loc : CantUnwindLocs)
Parser.Note(Loc, ".cantunwind was specified here");
}
void emitHandlerDataLocNotes() const {
- for (const SMLoc &Loc : HandlerDataLocs)
+ for (SMLoc Loc : HandlerDataLocs)
Parser.Note(Loc, ".handlerdata was specified here");
}
diff --git a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
index 3e9666f586e0f..deef39407ea35 100644
--- a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
+++ b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
@@ -39,9 +39,9 @@ class M68kAsmParser : public MCTargetAsmParser {
#include "M68kGenAsmMatcher.inc"
// Helpers for Match&Emit.
- bool invalidOperand(const SMLoc &Loc, const OperandVector &Operands,
+ bool invalidOperand(SMLoc Loc, const OperandVector &Operands,
const uint64_t &ErrorInfo);
- bool missingFeature(const SMLoc &Loc, const uint64_t &ErrorInfo);
+ bool missingFeature(SMLoc Loc, const uint64_t &ErrorInfo);
bool emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const;
bool parseRegisterName(MCRegister &RegNo, SMLoc Loc, StringRef RegisterName);
ParseStatus parseRegister(MCRegister &RegNo);
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 253b737ce2290..a8908d4b710e6 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1247,7 +1247,7 @@ class X86AsmParser : public MCTargetAsmParser {
/// return false if no parsing errors occurred, true otherwise.
bool HandleAVX512Operand(OperandVector &Operands);
- bool ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc);
+ bool ParseZ(std::unique_ptr<X86Operand> &Z, SMLoc StartLoc);
bool is64BitMode() const {
// FIXME: Can tablegen auto-generate this?
@@ -2907,8 +2907,7 @@ X86::CondCode X86AsmParser::ParseConditionCode(StringRef CC) {
// true on failure, false otherwise
// If no {z} mark was found - Parser doesn't advance
-bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z,
- const SMLoc &StartLoc) {
+bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z, SMLoc StartLoc) {
MCAsmParser &Parser = getParser();
// Assuming we are just pass the '{' mark, quering the next token
// Searched for {z}, but none was found. Return false, as no parsing error was
diff --git a/llvm/utils/FileCheck/FileCheck.cpp b/llvm/utils/FileCheck/FileCheck.cpp
index 185b6b30994fc..305c28b4c7257 100644
--- a/llvm/utils/FileCheck/FileCheck.cpp
+++ b/llvm/utils/FileCheck/FileCheck.cpp
@@ -384,7 +384,7 @@ BuildInputAnnotations(const SourceMgr &SM, unsigned CheckFileBufferID,
std::vector<InputAnnotation> &Annotations,
unsigned &LabelWidth) {
struct CompareSMLoc {
- bool operator()(const SMLoc &LHS, const SMLoc &RHS) const {
+ bool operator()(SMLoc LHS, SMLoc RHS) const {
return LHS.getPointer() < RHS.getPointer();
}
};
|
|
Could this have caused the failure in https://lab.llvm.org/buildbot/#/builders/27/builds/16657? |
|
Yeah, looking at it. It looks like this is not built in the github CI. |
|
Fix here: #160926 |
jurahul
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Fix M68k build failures caused by llvm/llvm-project#160797
Yes, I think it's an experimental target. You have to explicitly enable it. |
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…vm#160797) SMLoc itself encapsulates just a pointer, so there is no need to pass or return it by reference.
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Fix M68k build failures caused by llvm#160797
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SMLoc itself encapsulates just a pointer, so there is no need to pass or return it by reference.