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[NFC][LLVM] Pass/return SMLoc by value instead of const reference #160797

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Merged
merged 3 commits into from
Sep 26, 2025
+23 −26
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[NFC][LLVM] Pass/return SMLoc by value instead of const reference #160797

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7118157
[NFC][LLVM] Pass/return SMLoc by value instead of const reference
jurahul Sep 26, 2025
05d43f6
Merge branch 'main' into nfc_smloc_byval
jurahul Sep 26, 2025
a4a2d01
Merge branch 'main' into nfc_smloc_byval
jurahul Sep 26, 2025
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4 changes: 2 additions & 2 deletions llvm/include/llvm/Support/SMLoc.h
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Expand Up @@ -28,8 +28,8 @@ class SMLoc {

constexpr bool isValid() const { return Ptr != nullptr; }

constexpr bool operator==(const SMLoc &RHS) const { return RHS.Ptr == Ptr; }
constexpr bool operator!=(const SMLoc &RHS) const { return RHS.Ptr != Ptr; }
constexpr bool operator==(SMLoc RHS) const { return RHS.Ptr == Ptr; }
constexpr bool operator!=(SMLoc RHS) const { return RHS.Ptr != Ptr; }

constexpr const char *getPointer() const { return Ptr; }

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2 changes: 1 addition & 1 deletion llvm/include/llvm/TableGen/Record.h
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Expand Up @@ -1577,7 +1577,7 @@ class RecordVal {
}

/// Get the source location of the point where the field was defined.
const SMLoc &getLoc() const { return Loc; }
SMLoc getLoc() const { return Loc; }

/// Is this a field where nonconcrete values are okay?
bool isNonconcreteOK() const {
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2 changes: 1 addition & 1 deletion llvm/lib/MC/MCSFrame.cpp
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Expand Up @@ -200,7 +200,7 @@ class SFrameEmitterImpl {
return false;
}

bool setCFAOffset(SFrameFRE &FRE, const SMLoc &Loc, size_t Offset) {
bool setCFAOffset(SFrameFRE &FRE, SMLoc Loc, size_t Offset) {
if (!FRE.CFARegSet) {
Streamer.getContext().reportWarning(
Loc, "adjusting CFA offset without a base register. "
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24 changes: 11 additions & 13 deletions llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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Expand Up @@ -1807,7 +1807,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
const OperandVector &Operands) const;
SMLoc getInstLoc(const OperandVector &Operands) const;

bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
bool validateInstruction(const MCInst &Inst, SMLoc IDLoc,
const OperandVector &Operands);
bool validateOffset(const MCInst &Inst, const OperandVector &Operands);
bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
Expand All @@ -1824,8 +1825,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateMIMGAtomicDMask(const MCInst &Inst);
bool validateMIMGGatherDMask(const MCInst &Inst);
bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);
bool validateMIMGDataSize(const MCInst &Inst, const SMLoc &IDLoc);
bool validateMIMGAddrSize(const MCInst &Inst, const SMLoc &IDLoc);
bool validateMIMGDataSize(const MCInst &Inst, SMLoc IDLoc);
bool validateMIMGAddrSize(const MCInst &Inst, SMLoc IDLoc);
bool validateMIMGD16(const MCInst &Inst);
bool validateMIMGDim(const MCInst &Inst, const OperandVector &Operands);
bool validateTensorR128(const MCInst &Inst);
Expand All @@ -1847,7 +1848,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateDivScale(const MCInst &Inst);
bool validateWaitCnt(const MCInst &Inst, const OperandVector &Operands);
bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
const SMLoc &IDLoc);
SMLoc IDLoc);
bool validateTHAndScopeBits(const MCInst &Inst, const OperandVector &Operands,
const unsigned CPol);
bool validateTFE(const MCInst &Inst, const OperandVector &Operands);
Expand All @@ -1864,7 +1865,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool isSupportedMnemo(StringRef Mnemo,
const FeatureBitset &FBS,
ArrayRef<unsigned> Variants);
bool checkUnsupportedInstruction(StringRef Name, const SMLoc &IDLoc);
bool checkUnsupportedInstruction(StringRef Name, SMLoc IDLoc);

bool isId(const StringRef Id) const;
bool isId(const AsmToken &Token, const StringRef Id) const;
Expand Down Expand Up @@ -4087,8 +4088,7 @@ bool AMDGPUAsmParser::validateIntClampSupported(const MCInst &Inst) {
constexpr uint64_t MIMGFlags =
SIInstrFlags::MIMG | SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE;

bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,
const SMLoc &IDLoc) {
bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst, SMLoc IDLoc) {

const unsigned Opc = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opc);
Expand Down Expand Up @@ -4135,8 +4135,7 @@ bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,
return false;
}

bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
const SMLoc &IDLoc) {
bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst, SMLoc IDLoc) {
const unsigned Opc = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opc);

Expand Down Expand Up @@ -5344,7 +5343,7 @@ bool AMDGPUAsmParser::validateGWS(const MCInst &Inst,

bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
const OperandVector &Operands,
const SMLoc &IDLoc) {
SMLoc IDLoc) {
int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
AMDGPU::OpName::cpol);
if (CPolPos == -1)
Expand Down Expand Up @@ -5541,8 +5540,7 @@ bool AMDGPUAsmParser::validateWMMA(const MCInst &Inst,
validateFmt(AMDGPU::OpName::matrix_b_fmt, AMDGPU::OpName::src1);
}

bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
const SMLoc &IDLoc,
bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst, SMLoc IDLoc,
const OperandVector &Operands) {
if (!validateLdsDirect(Inst, Operands))
return false;
Expand Down Expand Up @@ -5704,7 +5702,7 @@ bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,
}

bool AMDGPUAsmParser::checkUnsupportedInstruction(StringRef Mnemo,
const SMLoc &IDLoc) {
SMLoc IDLoc) {
FeatureBitset FBS = ComputeAvailableFeatures(getFeatureBits());

// Check if requested instruction variant is supported.
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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Expand Up @@ -135,17 +135,17 @@ class UnwindContext {
MCRegister getFPReg() const { return FPReg; }

void emitFnStartLocNotes() const {
for (const SMLoc &Loc : FnStartLocs)
for (SMLoc Loc : FnStartLocs)
Parser.Note(Loc, ".fnstart was specified here");
}

void emitCantUnwindLocNotes() const {
for (const SMLoc &Loc : CantUnwindLocs)
for (SMLoc Loc : CantUnwindLocs)
Parser.Note(Loc, ".cantunwind was specified here");
}

void emitHandlerDataLocNotes() const {
for (const SMLoc &Loc : HandlerDataLocs)
for (SMLoc Loc : HandlerDataLocs)
Parser.Note(Loc, ".handlerdata was specified here");
}

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4 changes: 2 additions & 2 deletions llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
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Expand Up @@ -39,9 +39,9 @@ class M68kAsmParser : public MCTargetAsmParser {
#include "M68kGenAsmMatcher.inc"

// Helpers for Match&Emit.
bool invalidOperand(const SMLoc &Loc, const OperandVector &Operands,
bool invalidOperand(SMLoc Loc, const OperandVector &Operands,
const uint64_t &ErrorInfo);
bool missingFeature(const SMLoc &Loc, const uint64_t &ErrorInfo);
bool missingFeature(SMLoc Loc, const uint64_t &ErrorInfo);
bool emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const;
bool parseRegisterName(MCRegister &RegNo, SMLoc Loc, StringRef RegisterName);
ParseStatus parseRegister(MCRegister &RegNo);
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5 changes: 2 additions & 3 deletions llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
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Expand Up @@ -1247,7 +1247,7 @@ class X86AsmParser : public MCTargetAsmParser {
/// return false if no parsing errors occurred, true otherwise.
bool HandleAVX512Operand(OperandVector &Operands);

bool ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc);
bool ParseZ(std::unique_ptr<X86Operand> &Z, SMLoc StartLoc);

bool is64BitMode() const {
// FIXME: Can tablegen auto-generate this?
Expand Down Expand Up @@ -2907,8 +2907,7 @@ X86::CondCode X86AsmParser::ParseConditionCode(StringRef CC) {

// true on failure, false otherwise
// If no {z} mark was found - Parser doesn't advance
bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z,
const SMLoc &StartLoc) {
bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z, SMLoc StartLoc) {
MCAsmParser &Parser = getParser();
// Assuming we are just pass the '{' mark, quering the next token
// Searched for {z}, but none was found. Return false, as no parsing error was
Expand Down
2 changes: 1 addition & 1 deletion llvm/utils/FileCheck/FileCheck.cpp
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Expand Up @@ -384,7 +384,7 @@ BuildInputAnnotations(const SourceMgr &SM, unsigned CheckFileBufferID,
std::vector<InputAnnotation> &Annotations,
unsigned &LabelWidth) {
struct CompareSMLoc {
bool operator()(const SMLoc &LHS, const SMLoc &RHS) const {
bool operator()(SMLoc LHS, SMLoc RHS) const {
return LHS.getPointer() < RHS.getPointer();
}
};
Expand Down