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[DAG] Add ComputeNumSignBits(FREEZE(X)) handling #161507

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Merged
merged 5 commits into from
Oct 2, 2025
Merged

[DAG] Add ComputeNumSignBits(FREEZE(X)) handling #161507

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6f29ad5
[DAG] Add ComputeNumSignBits(FREEZE(X)) handling
RKSimon Oct 1, 2025
2cc31ec
Merge branch 'main' into dag-computenumsignbits-freeze
RKSimon Oct 1, 2025
14588c9
Merge branch 'main' into dag-computenumsignbits-freeze
bjope Oct 2, 2025
3e4e735
Merge branch 'main' into dag-computenumsignbits-freeze
bjope Oct 2, 2025
b2a61c4
Merge branch 'main' into dag-computenumsignbits-freeze
RKSimon Oct 2, 2025
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5 changes: 5 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4762,6 +4762,11 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
case ISD::AssertZext:
Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
return VTBits-Tmp;
case ISD::FREEZE:
if (isGuaranteedNotToBeUndefOrPoison(Op.getOperand(0), DemandedElts,
/*PoisonOnly=*/false))
return ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
break;
case ISD::MERGE_VALUES:
return ComputeNumSignBits(Op.getOperand(Op.getResNo()), DemandedElts,
Depth + 1);
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6 changes: 0 additions & 6 deletions llvm/test/CodeGen/AArch64/freeze.ll
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Expand Up @@ -466,15 +466,12 @@ define <8 x i16> @freeze_urhadd(<8 x i16> %a0, <8 x i16> %a1) {
ret <8 x i16> %masked
}

; TODO: Unnecessary sext_inreg
define <8 x i16> @freeze_shadd(<8 x i8> %a0, <8 x i16> %a1) {
; CHECK-LABEL: freeze_shadd:
; CHECK: // %bb.0:
; CHECK-NEXT: sshll v0.8h, v0.8b, #0
; CHECK-NEXT: sshr v1.8h, v1.8h, #8
; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h
; CHECK-NEXT: shl v0.8h, v0.8h, #8
; CHECK-NEXT: sshr v0.8h, v0.8h, #8
; CHECK-NEXT: ret
%x0 = sext <8 x i8> %a0 to <8 x i16>
%x1 = ashr <8 x i16> %a1, splat (i16 8)
Expand All @@ -485,15 +482,12 @@ define <8 x i16> @freeze_shadd(<8 x i8> %a0, <8 x i16> %a1) {
ret <8 x i16> %sext
}

; TODO: Unnecessary sext_inreg
define <8 x i16> @freeze_srhadd(<8 x i8> %a0, <8 x i16> %a1) {
; CHECK-LABEL: freeze_srhadd:
; CHECK: // %bb.0:
; CHECK-NEXT: sshll v0.8h, v0.8b, #0
; CHECK-NEXT: sshr v1.8h, v1.8h, #8
; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h
; CHECK-NEXT: shl v0.8h, v0.8h, #8
; CHECK-NEXT: sshr v0.8h, v0.8h, #8
; CHECK-NEXT: ret
%x0 = sext <8 x i8> %a0 to <8 x i16>
%x1 = ashr <8 x i16> %a1, splat (i16 8)
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