[TableGen][MC] Pass a MCSubtargetInfo instance into resolveVariantSchedClassImpl

[mshockwave]

Target_MC::resolveVariantSchedClassImpl is the implementation function for TargetGenMCSubtargetInfo::resolveVariantSchedClass. Despite being only called by resolveVariantSchedClass, resolveVariantSchedClassImpl is still a standalone function that cannot access a MCSubtargetInfo through this (i.e. TargetGenMCSubtargetInfo). And having access to a MCSubtargetInfo could be useful for some (future) SchedPredicate.

This patch modifies TableGen to generate resolveVariantSchedClassImpl with an additional MCSubtargetInfo argument passing in. Note that this does not change any public interface in either TargetGenMCSubtargetInfo or MCSubtargetInfo, as resolveVariantSchedClassImpl is basically an internal function.

[llvmbot]

@llvm/pr-subscribers-tablegen

Author: Min-Yih Hsu (mshockwave)

Changes

Target_MC::resolveVariantSchedClassImpl is the implementation function for TargetGenMCSubtargetInfo::resolveVariantSchedClass. Despite being only called by resolveVariantSchedClass, resolveVariantSchedClassImpl is still a standalone function that cannot access a MCSubtargetInfo through this (i.e. TargetGenMCSubtargetInfo). And having access to a MCSubtargetInfo could be useful for some (future) SchedPredicate.

This patch modifies TableGen to generate resolveVariantSchedClassImpl with an additional MCSubtargetInfo argument passing in. Note that this does not change any public interface in either TargetGenMCSubtargetInfo or MCSubtargetInfo, as resolveVariantSchedClassImpl is basically an internal function.

---

Full diff: https://github.com/llvm/llvm-project/pull/161886.diff

2 Files Affected:

• (added) llvm/test/TableGen/ResolveSchedClass.td (+18)
• (modified) llvm/utils/TableGen/SubtargetEmitter.cpp (+6-4)

diff --git a/llvm/test/TableGen/ResolveSchedClass.td b/llvm/test/TableGen/ResolveSchedClass.td
new file mode 100644
index 0000000000000..8c9ef1eab3566
--- /dev/null
+++ b/llvm/test/TableGen/ResolveSchedClass.td
@@ -0,0 +1,18 @@
+// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s -o - | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+def TestTargetInstrInfo : InstrInfo;
+
+def TestTarget : Target {
+  let InstructionSet = TestTargetInstrInfo;
+}
+
+// CHECK:  unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
+// CHECK-NEXT:      const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID)
+
+// CHECK: unsigned resolveVariantSchedClass(unsigned SchedClass,
+// CHECK-NEXT:    const MCInst *MI, const MCInstrInfo *MCII,
+// CHECK-NEXT:    unsigned CPUID) const override {
+// CHECK-NEXT:   return TestTarget_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
+// CHECK-NEXT: }
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 0f42d49a6bea1..b0a309cdbfef8 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -1761,7 +1761,7 @@ void SubtargetEmitter::emitSchedModelHelpers(const std::string &ClassName,
      << "\n::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,"
      << " const MCInstrInfo *MCII, unsigned CPUID) const {\n"
      << "  return " << Target << "_MC"
-     << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);\n"
+     << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);\n"
      << "} // " << ClassName << "::resolveVariantSchedClass\n\n";
 
   STIPredicateExpander PE(Target, /*Indent=*/0);
@@ -1923,7 +1923,8 @@ void SubtargetEmitter::parseFeaturesFunction(raw_ostream &OS) {
 void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
   OS << "namespace " << Target << "_MC {\n"
      << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,\n"
-     << "    const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {\n";
+     << "    const MCInst *MI, const MCInstrInfo *MCII, "
+     << "const MCSubtargetInfo &STI, unsigned CPUID) {\n";
   emitSchedModelHelpersImpl(OS, /* OnlyExpandMCPredicates */ true);
   OS << "}\n";
   OS << "} // end namespace " << Target << "_MC\n\n";
@@ -1945,7 +1946,7 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
      << "      const MCInst *MI, const MCInstrInfo *MCII,\n"
      << "      unsigned CPUID) const override {\n"
      << "    return " << Target << "_MC"
-     << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);\n";
+     << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);\n";
   OS << "  }\n";
   if (TGT.getHwModes().getNumModeIds() > 1) {
     OS << "  unsigned getHwModeSet() const override;\n";
@@ -2073,7 +2074,8 @@ void SubtargetEmitter::run(raw_ostream &OS) {
   OS << "class DFAPacketizer;\n";
   OS << "namespace " << Target << "_MC {\n"
      << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,"
-     << " const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);\n"
+     << " const MCInst *MI, const MCInstrInfo *MCII, "
+     << "const MCSubtargetInfo &STI, unsigned CPUID);\n"
      << "} // end namespace " << Target << "_MC\n\n";
   OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
      << "  explicit " << ClassName << "(const Triple &TT, StringRef CPU, "

[topperc]

LGTM