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[TableGen][MC] Pass a MCSubtargetInfo instance into resolveVariantSchedClassImpl #161886

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Merged
merged 1 commit into from
Oct 4, 2025
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[TableGen][MC] Pass a MCSubtargetInfo instance into resolveVariantSchedClassImpl #161886

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18 changes: 18 additions & 0 deletions llvm/test/TableGen/ResolveSchedClass.td
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Original file line number Diff line number Diff line change
@@ -0,0 +1,18 @@
// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s -o - | FileCheck %s

include "llvm/Target/Target.td"

def TestTargetInstrInfo : InstrInfo;

def TestTarget : Target {
let InstructionSet = TestTargetInstrInfo;
}

// CHECK: unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
// CHECK-NEXT: const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID)

// CHECK: unsigned resolveVariantSchedClass(unsigned SchedClass,
// CHECK-NEXT: const MCInst *MI, const MCInstrInfo *MCII,
// CHECK-NEXT: unsigned CPUID) const override {
// CHECK-NEXT: return TestTarget_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
// CHECK-NEXT: }
10 changes: 6 additions & 4 deletions llvm/utils/TableGen/SubtargetEmitter.cpp
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Expand Up @@ -1761,7 +1761,7 @@ void SubtargetEmitter::emitSchedModelHelpers(const std::string &ClassName,
<< "\n::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,"
<< " const MCInstrInfo *MCII, unsigned CPUID) const {\n"
<< " return " << Target << "_MC"
<< "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);\n"
<< "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);\n"
<< "} // " << ClassName << "::resolveVariantSchedClass\n\n";

STIPredicateExpander PE(Target, /*Indent=*/0);
Expand Down Expand Up @@ -1923,7 +1923,8 @@ void SubtargetEmitter::parseFeaturesFunction(raw_ostream &OS) {
void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
OS << "namespace " << Target << "_MC {\n"
<< "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,\n"
<< " const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {\n";
<< " const MCInst *MI, const MCInstrInfo *MCII, "
<< "const MCSubtargetInfo &STI, unsigned CPUID) {\n";
emitSchedModelHelpersImpl(OS, /* OnlyExpandMCPredicates */ true);
OS << "}\n";
OS << "} // end namespace " << Target << "_MC\n\n";
Expand All @@ -1945,7 +1946,7 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
<< " const MCInst *MI, const MCInstrInfo *MCII,\n"
<< " unsigned CPUID) const override {\n"
<< " return " << Target << "_MC"
<< "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);\n";
<< "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);\n";
OS << " }\n";
if (TGT.getHwModes().getNumModeIds() > 1) {
OS << " unsigned getHwModeSet() const override;\n";
Expand Down Expand Up @@ -2073,7 +2074,8 @@ void SubtargetEmitter::run(raw_ostream &OS) {
OS << "class DFAPacketizer;\n";
OS << "namespace " << Target << "_MC {\n"
<< "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,"
<< " const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);\n"
<< " const MCInst *MI, const MCInstrInfo *MCII, "
<< "const MCSubtargetInfo &STI, unsigned CPUID);\n"
<< "} // end namespace " << Target << "_MC\n\n";
OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
<< " explicit " << ClassName << "(const Triple &TT, StringRef CPU, "
Expand Down