[msan] Precommit MSan Arm NEON vst tests #98247

thurstond · 2024-07-09T23:44:51Z

These tests show that MSan currently does not handle vst (or vld) correctly.

llvmbot · 2024-07-09T23:45:20Z

@llvm/pr-subscribers-clang

Author: Thurston Dang (thurstond)

Changes

These tests show that MSan currently does not handle vst (or vld) correctly.

Patch is 1.22 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/98247.diff

2 Files Affected:

(added) clang/test/CodeGen/aarch64-neon-intrinsics-msan-vst.c (+1250)
(added) clang/test/CodeGen/aarch64-neon-intrinsics-msan.c (+18071)

diff --git a/clang/test/CodeGen/aarch64-neon-intrinsics-msan-vst.c b/clang/test/CodeGen/aarch64-neon-intrinsics-msan-vst.c
new file mode 100644
index 0000000000000..c0cfe093a1a18
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-neon-intrinsics-msan-vst.c
@@ -0,0 +1,1250 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
+// RUN:     -S \
+// RUN:  -emit-llvm -o - %s -fsanitize=memory \
+// RUN: | FileCheck %s
+
+// REQUIRES: aarch64-registered-target || arm-registered-target
+
+#include <arm_neon.h>
+#include <sanitizer/msan_interface.h>
+
+// CHECK-LABEL: define dso_local noundef i32 @test_vst1(
+// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.donothing()
+// CHECK-NEXT:    [[__P0_ADDR_I:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[TMP0:%.*]] = ptrtoint ptr [[__P0_ADDR_I]] to i64
+// CHECK-NEXT:    [[TMP1:%.*]] = xor i64 [[TMP0]], 193514046488576
+// CHECK-NEXT:    [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr
+// CHECK-NEXT:    call void @llvm.memset.p0.i64(ptr align 2 [[TMP2]], i8 -1, i64 2, i1 false)
+// CHECK-NEXT:    [[__RET_I:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    [[DOTCOMPOUNDLITERAL_I:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[DOTCOMPOUNDLITERAL_I]] to i64
+// CHECK-NEXT:    [[TMP4:%.*]] = xor i64 [[TMP3]], 193514046488576
+// CHECK-NEXT:    [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+// CHECK-NEXT:    call void @llvm.memset.p0.i64(ptr align 16 [[TMP5]], i8 -1, i64 16, i1 false)
+// CHECK-NEXT:    [[VEC1:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    [[DST1:%.*]] = alloca [8 x i16], align 2
+// CHECK-NEXT:    [[__S1:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    [[SUM:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[I:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    call void @llvm.lifetime.start.p0(i64 16, ptr [[VEC1]]) #[[ATTR4:[0-9]+]]
+// CHECK-NEXT:    [[TMP6:%.*]] = ptrtoint ptr [[VEC1]] to i64
+// CHECK-NEXT:    [[TMP7:%.*]] = xor i64 [[TMP6]], 193514046488576
+// CHECK-NEXT:    [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
+// CHECK-NEXT:    call void @llvm.memset.p0.i64(ptr align 16 [[TMP8]], i8 -1, i64 16, i1 false)
+// CHECK-NEXT:    [[TMP9:%.*]] = ptrtoint ptr [[__P0_ADDR_I]] to i64
+// CHECK-NEXT:    [[TMP10:%.*]] = xor i64 [[TMP9]], 193514046488576
+// CHECK-NEXT:    [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr
+// CHECK-NEXT:    store i16 0, ptr [[TMP11]], align 2
+// CHECK-NEXT:    store i16 15, ptr [[__P0_ADDR_I]], align 2
+// CHECK-NEXT:    call void @llvm.lifetime.start.p0(i64 16, ptr [[__RET_I]]) #[[ATTR4]]
+// CHECK-NEXT:    [[TMP12:%.*]] = ptrtoint ptr [[__RET_I]] to i64
+// CHECK-NEXT:    [[TMP13:%.*]] = xor i64 [[TMP12]], 193514046488576
+// CHECK-NEXT:    [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr
+// CHECK-NEXT:    call void @llvm.memset.p0.i64(ptr align 16 [[TMP14]], i8 -1, i64 16, i1 false)
+// CHECK-NEXT:    [[TMP15:%.*]] = load i16, ptr [[__P0_ADDR_I]], align 2
+// CHECK-NEXT:    [[TMP16:%.*]] = ptrtoint ptr [[__P0_ADDR_I]] to i64
+// CHECK-NEXT:    [[TMP17:%.*]] = xor i64 [[TMP16]], 193514046488576
+// CHECK-NEXT:    [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr
+// CHECK-NEXT:    [[_MSLD:%.*]] = load i16, ptr [[TMP18]], align 2
+// CHECK-NEXT:    [[_MSPROP:%.*]] = insertelement <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, i16 [[_MSLD]], i32 0
+// CHECK-NEXT:    [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[TMP15]], i32 0
+// CHECK-NEXT:    [[TMP19:%.*]] = load i16, ptr [[__P0_ADDR_I]], align 2
+// CHECK-NEXT:    [[TMP20:%.*]] = ptrtoint ptr [[__P0_ADDR_I]] to i64
+// CHECK-NEXT:    [[TMP21:%.*]] = xor i64 [[TMP20]], 193514046488576
+// CHECK-NEXT:    [[TMP22:%.*]] = inttoptr i64 [[TMP21]] to ptr
+// CHECK-NEXT:    [[_MSLD2:%.*]] = load i16, ptr [[TMP22]], align 2
+// CHECK-NEXT:    [[_MSPROP3:%.*]] = insertelement <8 x i16> [[_MSPROP]], i16 [[_MSLD2]], i32 1
+// CHECK-NEXT:    [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[TMP19]], i32 1
+// CHECK-NEXT:    [[TMP23:%.*]] = load i16, ptr [[__P0_ADDR_I]], align 2
+// CHECK-NEXT:    [[TMP24:%.*]] = ptrtoint ptr [[__P0_ADDR_I]] to i64
+// CHECK-NEXT:    [[TMP25:%.*]] = xor i64 [[TMP24]], 193514046488576
+// CHECK-NEXT:    [[TMP26:%.*]] = inttoptr i64 [[TMP25]] to ptr
+// CHECK-NEXT:    [[_MSLD4:%.*]] = load i16, ptr [[TMP26]], align 2
+// CHECK-NEXT:    [[_MSPROP5:%.*]] = insertelement <8 x i16> [[_MSPROP3]], i16 [[_MSLD4]], i32 2
+// CHECK-NEXT:    [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[TMP23]], i32 2
+// CHECK-NEXT:    [[TMP27:%.*]] = load i16, ptr [[__P0_ADDR_I]], align 2
+// CHECK-NEXT:    [[TMP28:%.*]] = ptrtoint ptr [[__P0_ADDR_I]] to i64
+// CHECK-NEXT:    [[TMP29:%.*]] = xor i64 [[TMP28]], 193514046488576
+// CHECK-NEXT:    [[TMP30:%.*]] = inttoptr i64 [[TMP29]] to ptr
+// CHECK-NEXT:    [[_MSLD6:%.*]] = load i16, ptr [[TMP30]], align 2
+// CHECK-NEXT:    [[_MSPROP7:%.*]] = insertelement <8 x i16> [[_MSPROP5]], i16 [[_MSLD6]], i32 3
+// CHECK-NEXT:    [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[TMP27]], i32 3
+// CHECK-NEXT:    [[TMP31:%.*]] = load i16, ptr [[__P0_ADDR_I]], align 2
+// CHECK-NEXT:    [[TMP32:%.*]] = ptrtoint ptr [[__P0_ADDR_I]] to i64
+// CHECK-NEXT:    [[TMP33:%.*]] = xor i64 [[TMP32]], 193514046488576
+// CHECK-NEXT:    [[TMP34:%.*]] = inttoptr i64 [[TMP33]] to ptr
+// CHECK-NEXT:    [[_MSLD8:%.*]] = load i16, ptr [[TMP34]], align 2
+// CHECK-NEXT:    [[_MSPROP9:%.*]] = insertelement <8 x i16> [[_MSPROP7]], i16 [[_MSLD8]], i32 4
+// CHECK-NEXT:    [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[TMP31]], i32 4
+// CHECK-NEXT:    [[TMP35:%.*]] = load i16, ptr [[__P0_ADDR_I]], align 2
+// CHECK-NEXT:    [[TMP36:%.*]] = ptrtoint ptr [[__P0_ADDR_I]] to i64
+// CHECK-NEXT:    [[TMP37:%.*]] = xor i64 [[TMP36]], 193514046488576
+// CHECK-NEXT:    [[TMP38:%.*]] = inttoptr i64 [[TMP37]] to ptr
+// CHECK-NEXT:    [[_MSLD10:%.*]] = load i16, ptr [[TMP38]], align 2
+// CHECK-NEXT:    [[_MSPROP11:%.*]] = insertelement <8 x i16> [[_MSPROP9]], i16 [[_MSLD10]], i32 5
+// CHECK-NEXT:    [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[TMP35]], i32 5
+// CHECK-NEXT:    [[TMP39:%.*]] = load i16, ptr [[__P0_ADDR_I]], align 2
+// CHECK-NEXT:    [[TMP40:%.*]] = ptrtoint ptr [[__P0_ADDR_I]] to i64
+// CHECK-NEXT:    [[TMP41:%.*]] = xor i64 [[TMP40]], 193514046488576
+// CHECK-NEXT:    [[TMP42:%.*]] = inttoptr i64 [[TMP41]] to ptr
+// CHECK-NEXT:    [[_MSLD12:%.*]] = load i16, ptr [[TMP42]], align 2
+// CHECK-NEXT:    [[_MSPROP13:%.*]] = insertelement <8 x i16> [[_MSPROP11]], i16 [[_MSLD12]], i32 6
+// CHECK-NEXT:    [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[TMP39]], i32 6
+// CHECK-NEXT:    [[TMP43:%.*]] = load i16, ptr [[__P0_ADDR_I]], align 2
+// CHECK-NEXT:    [[TMP44:%.*]] = ptrtoint ptr [[__P0_ADDR_I]] to i64
+// CHECK-NEXT:    [[TMP45:%.*]] = xor i64 [[TMP44]], 193514046488576
+// CHECK-NEXT:    [[TMP46:%.*]] = inttoptr i64 [[TMP45]] to ptr
+// CHECK-NEXT:    [[_MSLD14:%.*]] = load i16, ptr [[TMP46]], align 2
+// CHECK-NEXT:    [[_MSPROP15:%.*]] = insertelement <8 x i16> [[_MSPROP13]], i16 [[_MSLD14]], i32 7
+// CHECK-NEXT:    [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[TMP43]], i32 7
+// CHECK-NEXT:    [[TMP47:%.*]] = ptrtoint ptr [[DOTCOMPOUNDLITERAL_I]] to i64
+// CHECK-NEXT:    [[TMP48:%.*]] = xor i64 [[TMP47]], 193514046488576
+// CHECK-NEXT:    [[TMP49:%.*]] = inttoptr i64 [[TMP48]] to ptr
+// CHECK-NEXT:    store <8 x i16> [[_MSPROP15]], ptr [[TMP49]], align 16
+// CHECK-NEXT:    store <8 x i16> [[VECINIT7_I]], ptr [[DOTCOMPOUNDLITERAL_I]], align 16
+// CHECK-NEXT:    [[TMP50:%.*]] = load <8 x i16>, ptr [[DOTCOMPOUNDLITERAL_I]], align 16
+// CHECK-NEXT:    [[TMP51:%.*]] = ptrtoint ptr [[DOTCOMPOUNDLITERAL_I]] to i64
+// CHECK-NEXT:    [[TMP52:%.*]] = xor i64 [[TMP51]], 193514046488576
+// CHECK-NEXT:    [[TMP53:%.*]] = inttoptr i64 [[TMP52]] to ptr
+// CHECK-NEXT:    [[_MSLD16:%.*]] = load <8 x i16>, ptr [[TMP53]], align 16
+// CHECK-NEXT:    [[TMP54:%.*]] = ptrtoint ptr [[__RET_I]] to i64
+// CHECK-NEXT:    [[TMP55:%.*]] = xor i64 [[TMP54]], 193514046488576
+// CHECK-NEXT:    [[TMP56:%.*]] = inttoptr i64 [[TMP55]] to ptr
+// CHECK-NEXT:    store <8 x i16> [[_MSLD16]], ptr [[TMP56]], align 16
+// CHECK-NEXT:    store <8 x i16> [[TMP50]], ptr [[__RET_I]], align 16
+// CHECK-NEXT:    [[TMP57:%.*]] = load <8 x i16>, ptr [[__RET_I]], align 16
+// CHECK-NEXT:    [[TMP58:%.*]] = ptrtoint ptr [[__RET_I]] to i64
+// CHECK-NEXT:    [[TMP59:%.*]] = xor i64 [[TMP58]], 193514046488576
+// CHECK-NEXT:    [[TMP60:%.*]] = inttoptr i64 [[TMP59]] to ptr
+// CHECK-NEXT:    [[_MSLD17:%.*]] = load <8 x i16>, ptr [[TMP60]], align 16
+// CHECK-NEXT:    call void @llvm.lifetime.end.p0(i64 16, ptr [[__RET_I]]) #[[ATTR4]]
+// CHECK-NEXT:    [[TMP61:%.*]] = ptrtoint ptr [[VEC1]] to i64
+// CHECK-NEXT:    [[TMP62:%.*]] = xor i64 [[TMP61]], 193514046488576
+// CHECK-NEXT:    [[TMP63:%.*]] = inttoptr i64 [[TMP62]] to ptr
+// CHECK-NEXT:    store <8 x i16> [[_MSLD17]], ptr [[TMP63]], align 16
+// CHECK-NEXT:    store <8 x i16> [[TMP57]], ptr [[VEC1]], align 16
+// CHECK-NEXT:    call void @llvm.lifetime.start.p0(i64 16, ptr [[DST1]]) #[[ATTR4]]
+// CHECK-NEXT:    [[TMP64:%.*]] = ptrtoint ptr [[DST1]] to i64
+// CHECK-NEXT:    [[TMP65:%.*]] = xor i64 [[TMP64]], 193514046488576
+// CHECK-NEXT:    [[TMP66:%.*]] = inttoptr i64 [[TMP65]] to ptr
+// CHECK-NEXT:    call void @llvm.memset.p0.i64(ptr align 2 [[TMP66]], i8 -1, i64 16, i1 false)
+// CHECK-NEXT:    call void @llvm.lifetime.start.p0(i64 16, ptr [[__S1]]) #[[ATTR4]]
+// CHECK-NEXT:    [[TMP67:%.*]] = ptrtoint ptr [[__S1]] to i64
+// CHECK-NEXT:    [[TMP68:%.*]] = xor i64 [[TMP67]], 193514046488576
+// CHECK-NEXT:    [[TMP69:%.*]] = inttoptr i64 [[TMP68]] to ptr
+// CHECK-NEXT:    call void @llvm.memset.p0.i64(ptr align 16 [[TMP69]], i8 -1, i64 16, i1 false)
+// CHECK-NEXT:    [[TMP70:%.*]] = load <8 x i16>, ptr [[VEC1]], align 16
+// CHECK-NEXT:    [[TMP71:%.*]] = ptrtoint ptr [[VEC1]] to i64
+// CHECK-NEXT:    [[TMP72:%.*]] = xor i64 [[TMP71]], 193514046488576
+// CHECK-NEXT:    [[TMP73:%.*]] = inttoptr i64 [[TMP72]] to ptr
+// CHECK-NEXT:    [[_MSLD18:%.*]] = load <8 x i16>, ptr [[TMP73]], align 16
+// CHECK-NEXT:    [[TMP74:%.*]] = ptrtoint ptr [[__S1]] to i64
+// CHECK-NEXT:    [[TMP75:%.*]] = xor i64 [[TMP74]], 193514046488576
+// CHECK-NEXT:    [[TMP76:%.*]] = inttoptr i64 [[TMP75]] to ptr
+// CHECK-NEXT:    store <8 x i16> [[_MSLD18]], ptr [[TMP76]], align 16
+// CHECK-NEXT:    store <8 x i16> [[TMP70]], ptr [[__S1]], align 16
+// CHECK-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [8 x i16], ptr [[DST1]], i64 0, i64 0
+// CHECK-NEXT:    [[TMP77:%.*]] = load <8 x i16>, ptr [[__S1]], align 16
+// CHECK-NEXT:    [[TMP78:%.*]] = ptrtoint ptr [[__S1]] to i64
+// CHECK-NEXT:    [[TMP79:%.*]] = xor i64 [[TMP78]], 193514046488576
+// CHECK-NEXT:    [[TMP80:%.*]] = inttoptr i64 [[TMP79]] to ptr
+// CHECK-NEXT:    [[_MSLD19:%.*]] = load <8 x i16>, ptr [[TMP80]], align 16
+// CHECK-NEXT:    [[TMP81:%.*]] = bitcast <8 x i16> [[_MSLD19]] to <16 x i8>
+// CHECK-NEXT:    [[TMP82:%.*]] = bitcast <8 x i16> [[TMP77]] to <16 x i8>
+// CHECK-NEXT:    [[TMP83:%.*]] = bitcast <16 x i8> [[TMP81]] to <8 x i16>
+// CHECK-NEXT:    [[TMP84:%.*]] = bitcast <16 x i8> [[TMP82]] to <8 x i16>
+// CHECK-NEXT:    [[TMP85:%.*]] = ptrtoint ptr [[ARRAYDECAY]] to i64
+// CHECK-NEXT:    [[TMP86:%.*]] = xor i64 [[TMP85]], 193514046488576
+// CHECK-NEXT:    [[TMP87:%.*]] = inttoptr i64 [[TMP86]] to ptr
+// CHECK-NEXT:    store <8 x i16> [[TMP83]], ptr [[TMP87]], align 2
+// CHECK-NEXT:    store <8 x i16> [[TMP84]], ptr [[ARRAYDECAY]], align 2
+// CHECK-NEXT:    call void @llvm.lifetime.end.p0(i64 16, ptr [[__S1]]) #[[ATTR4]]
+// CHECK-NEXT:    [[ARRAYDECAY1:%.*]] = getelementptr inbounds [8 x i16], ptr [[DST1]], i64 0, i64 0
+// CHECK-NEXT:    call void @__msan_print_shadow(ptr noundef [[ARRAYDECAY1]], i64 noundef 16)
+// CHECK-NEXT:    call void @llvm.lifetime.start.p0(i64 4, ptr [[SUM]]) #[[ATTR4]]
+// CHECK-NEXT:    [[TMP88:%.*]] = ptrtoint ptr [[SUM]] to i64
+// CHECK-NEXT:    [[TMP89:%.*]] = xor i64 [[TMP88]], 193514046488576
+// CHECK-NEXT:    [[TMP90:%.*]] = inttoptr i64 [[TMP89]] to ptr
+// CHECK-NEXT:    call void @llvm.memset.p0.i64(ptr align 4 [[TMP90]], i8 -1, i64 4, i1 false)
+// CHECK-NEXT:    [[TMP91:%.*]] = ptrtoint ptr [[SUM]] to i64
+// CHECK-NEXT:    [[TMP92:%.*]] = xor i64 [[TMP91]], 193514046488576
+// CHECK-NEXT:    [[TMP93:%.*]] = inttoptr i64 [[TMP92]] to ptr
+// CHECK-NEXT:    store i32 0, ptr [[TMP93]], align 4
+// CHECK-NEXT:    store i32 0, ptr [[SUM]], align 4
+// CHECK-NEXT:    call void @llvm.lifetime.start.p0(i64 4, ptr [[I]]) #[[ATTR4]]
+// CHECK-NEXT:    [[TMP94:%.*]] = ptrtoint ptr [[I]] to i64
+// CHECK-NEXT:    [[TMP95:%.*]] = xor i64 [[TMP94]], 193514046488576
+// CHECK-NEXT:    [[TMP96:%.*]] = inttoptr i64 [[TMP95]] to ptr
+// CHECK-NEXT:    call void @llvm.memset.p0.i64(ptr align 4 [[TMP96]], i8 -1, i64 4, i1 false)
+// CHECK-NEXT:    [[TMP97:%.*]] = ptrtoint ptr [[I]] to i64
+// CHECK-NEXT:    [[TMP98:%.*]] = xor i64 [[TMP97]], 193514046488576
+// CHECK-NEXT:    [[TMP99:%.*]] = inttoptr i64 [[TMP98]] to ptr
+// CHECK-NEXT:    store i32 0, ptr [[TMP99]], align 4
+// CHECK-NEXT:    store i32 0, ptr [[I]], align 4
+// CHECK-NEXT:    br label [[FOR_COND:%.*]]
+// CHECK:       for.cond:
+// CHECK-NEXT:    [[TMP100:%.*]] = load i32, ptr [[I]], align 4
+// CHECK-NEXT:    [[TMP101:%.*]] = ptrtoint ptr [[I]] to i64
+// CHECK-NEXT:    [[TMP102:%.*]] = xor i64 [[TMP101]], 193514046488576
+// CHECK-NEXT:    [[TMP103:%.*]] = inttoptr i64 [[TMP102]] to ptr
+// CHECK-NEXT:    [[_MSLD20:%.*]] = load i32, ptr [[TMP103]], align 4
+// CHECK-NEXT:    [[_MSPROP21:%.*]] = or i32 [[_MSLD20]], 0
+// CHECK-NEXT:    [[TMP104:%.*]] = icmp ne i32 [[_MSPROP21]], 0
+// CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP100]], 8
+// CHECK-NEXT:    br i1 [[TMP104]], label [[TMP105:%.*]], label [[TMP106:%.*]], !prof [[PROF2:![0-9]+]]
+// CHECK:       105:
+// CHECK-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7:[0-9]+]]
+// CHECK-NEXT:    unreachable
+// CHECK:       106:
+// CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]]
+// CHECK:       for.cond.cleanup:
+// CHECK-NEXT:    call void @llvm.lifetime.end.p0(i64 4, ptr [[I]]) #[[ATTR4]]
+// CHECK-NEXT:    br label [[FOR_END:%.*]]
+// CHECK:       for.body:
+// CHECK-NEXT:    [[TMP107:%.*]] = load i32, ptr [[I]], align 4
+// CHECK-NEXT:    [[TMP108:%.*]] = ptrtoint ptr [[I]] to i64
+// CHECK-NEXT:    [[TMP109:%.*]] = xor i64 [[TMP108]], 193514046488576
+// CHECK-NEXT:    [[TMP110:%.*]] = inttoptr i64 [[TMP109]] to ptr
+// CHECK-NEXT:    [[_MSLD22:%.*]] = load i32, ptr [[TMP110]], align 4
+// CHECK-NEXT:    [[_MSPROP23:%.*]] = sext i32 [[_MSLD22]] to i64
+// CHECK-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP107]] to i64
+// CHECK-NEXT:    [[_MSPROP24:%.*]] = or i64 0, [[_MSPROP23]]
+// CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [8 x i16], ptr [[DST1]], i64 0, i64 [[IDXPROM]]
+// CHECK-NEXT:    [[_MSCMP:%.*]] = icmp ne i64 [[_MSPROP24]], 0
+// CHECK-NEXT:    br i1 [[_MSCMP]], label [[TMP111:%.*]], label [[TMP112:%.*]], !prof [[PROF2]]
+// CHECK:       111:
+// CHECK-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
+// CHECK-NEXT:    unreachable
+// CHECK:       112:
+// CHECK-NEXT:    [[TMP113:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
+// CHECK-NEXT:    [[TMP114:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64
+// CHECK-NEXT:    [[TMP115:%.*]] = xor i64 [[TMP114]], 193514046488576
+// CHECK-NEXT:    [[TMP116:%.*]] = inttoptr i64 [[TMP115]] to ptr
+// CHECK-NEXT:    [[_MSLD25:%.*]] = load i16, ptr [[TMP116]], align 2
+// CHECK-NEXT:    [[_MSPROP26:%.*]] = sext i16 [[_MSLD25]] to i32
+// CHECK-NEXT:    [[CONV:%.*]] = sext i16 [[TMP113]] to i32
+// CHECK-NEXT:    [[TMP117:%.*]] = load i32, ptr [[SUM]], align 4
+// CHECK-NEXT:    [[TMP118:%.*]] = ptrtoint ptr [[SUM]] to i64
+// CHECK-NEXT:    [[TMP119:%.*]] = xor i64 [[TMP118]], 193514046488576
+// CHECK-NEXT:    [[TMP120:%.*]] = inttoptr i64 [[TMP119]] to ptr
+// CHECK-NEXT:    [[_MSLD27:%.*]] = load i32, ptr [[TMP120]], align 4
+// CHECK-NEXT:    [[_MSPROP28:%.*]] = or i32 [[_MSLD27]], [[_MSPROP26]]
+// CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP117]], [[CONV]]
+// CHECK-NEXT:    [[TMP121:%.*]] = ptrtoint ptr [[SUM]] to i64
+// CHECK-NEXT:    [[TMP122:%.*]] = xor i64 [[TMP121]], 193514046488576
+// CHECK-NEXT:    [[TMP123:%.*]] = inttoptr i64 [[TMP122]] to ptr
+// CHECK-NEXT:    store i32 [[_MSPROP28]], ptr [[TMP123]], align 4
+// CHECK-NEXT:    store i32 [[ADD]], ptr [[SUM]], align 4
+// CHECK-NEXT:    br label [[FOR_INC:%.*]]
+// CHECK:       for.inc:
+// CHECK-NEXT:    [[TMP124:%.*]] = load i32, ptr [[I]], align 4
+// CHECK-NEXT:    [[TMP125:%.*]] = ptrtoint ptr [[I]] to i64
+// CHECK-NEXT:    [[TMP126:%.*]] = xor i64 [[TMP125]], 193514046488576
+// CHECK-NEXT:    [[TMP127:%.*]] = inttoptr i64 [[TMP126]] to ptr
+// CHECK-NEXT:    [[_MSLD29:%.*]] = load i32, ptr [[TMP127]], align 4
+// CHECK-NEXT:    [[_MSPROP30:%.*]] = or i32 [[_MSLD29]], 0
+// CHECK-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP124]], 1
+// CHECK-NEXT:    [[TMP128:%.*]] = ptrtoint ptr [[I]] to i64
+// CHECK-NEXT:    [[TMP129:%.*]] = xor i64 [[TMP128]], 193514046488576
+// CHECK-NEXT:    [[TMP130:%.*]] = inttoptr i64 [[TMP129]] to ptr
+// CHECK-NEXT:    store i32 [[_MSPROP30]], ptr [[TMP130]], align 4
+// CHECK-NEXT:    store i32 [[INC]], ptr [[I]], align 4
+// CHECK-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
+// CHECK:       for.end:
+// CHECK-NEXT:    [[TMP131:%.*]] = load i32, ptr [[SUM]], align 4
+// CHECK-NEXT:    [[TMP132:%.*]] = ptrtoint ptr [[SUM]] to i64
+// CHECK-NEXT:    [[TMP133:%.*]] = xor i64 [[TMP132]], 193514046488576
+// CHECK-NEXT:    [[TMP134:%.*]] = inttoptr i64 [[TMP133]] to ptr
+// CHECK-NEXT:    [[_MSLD31:%.*]] = load i32, ptr [[TMP134]], align 4
+// CHECK-NEXT:    call void @llvm.lifetime.end.p0(i64 4, ptr [[SUM]]) #[[ATTR4]]
+// CHECK-NEXT:    call void @llvm.lifetime.end.p0(i64 16, ptr [[DST1]]) #[[ATTR4]]
+// CHECK-NEXT:    call void @llvm.lifetime.end.p0(i64 16, ptr [[VEC1]]) #[[ATTR4]]
+// CHECK-NEXT:    [[_MSCMP32:%.*]] = icmp ne i32 [[_MSLD31]], 0
+// CHECK-NEXT:    br i1 [[_MSCMP32]], label [[TMP135:%.*]], label [[TMP136:%.*]], !prof [[PROF2]]
+// CHECK:       135:
+// CHECK-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
+// CHECK-NEXT:    unreachable
+// CHECK:       136:
+// CHECK-NEXT:    ret i32 [[TMP131]]
+//
+int test_vst1(void) {
+  int16x8_t vec1;
+  vec1 = vdupq_n_s16(15);
+  int16_t dst1[8*1];
+  vst1q_s16(dst1, vec1);
+
+  __msan_print_shadow(dst1, sizeof(int16_t)*8*1);
+
+  int sum = 0;
+  for (int i = 0; i < 8*1; i++)
+    sum += dst1[i];
+
+  return sum;
+}
+
+// Initialization is only partial to make the shadows more interesting
+// CHECK-LABEL: define dso_local noundef i32 @test_vst2(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.donothing()
+// CHECK-NEXT:    [[__P0_ADDR_I:%.*]] = alloca i16, align 2
+// CHECK-NEXT:    [[TMP0:%.*]] = ptrtoint ptr [[__P0_ADDR_I]] to i64
+// CHECK-NEXT:    [[TMP1:%.*]] = xor i64 [[TMP0]], 193514046488576
+// CHECK-NEXT:    [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr
+// CHECK-NEXT:    call void @llvm.memset.p0.i64(ptr align 2 [[TMP2]], i8 -1, i64 2, i1 false)
+// CHECK-NEXT:    [[__RET_I:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    [[DOTCOMPOUNDLITERAL_I:%.*]] = alloca <8 x i16>, align 16
+// CHECK-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[DOTCOMPOUNDLITERAL_I]] to i64
+// CHECK-NEXT:    [[TMP4:%.*]] = xor i64 [[TMP3]], 193514046488576
+// CHECK-NEXT:    [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+// CHECK-NEXT:    call void @llvm.memset.p0.i64(ptr align 16 [[TMP5]], i8 -1, i64 16, i1 false)
+// CHECK-NEXT:    [[VEC2:%.*]] = alloca [[STRUCT_INT16X8X2_T:%.*]], align 16
+// CHECK-NEXT:    [[DST2:%.*]] = alloca [16 x i16], align 2
+// CHECK-NEXT:    [[__S1:%.*]] = alloca [[STRUCT_INT16X8X2_T]], align 16
+// CHECK-NEXT:    [[SUM:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[I:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    call void @llvm.lifetime.start.p0(i64 32, ptr [[VEC...
[truncated]

vitalybuka

Discussed offline, it should be IR tests

thurstond · 2024-07-16T18:15:38Z

Updated to IR tests

llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll

This adds support for vst{2,3,4}, which are not correctly handled by handleUnknownIntrinsic/handleVector{Load,Store}Intrinsic. This patch also updates the tests introduced in #98247 and #99555 --------- Co-authored-by: Vitaly Buka <vitalybuka@gmail.com>

These tests show that MSan currently does not handle vst (or vld) correctly.

…9360) This adds support for vst{2,3,4}, which are not correctly handled by handleUnknownIntrinsic/handleVector{Load,Store}Intrinsic. This patch also updates the tests introduced in llvm#98247 and llvm#99555 --------- Co-authored-by: Vitaly Buka <vitalybuka@gmail.com>

Summary: These tests show that MSan currently does not handle vst (or vld) correctly. Test Plan: Reviewers: Subscribers: Tasks: Tags: Differential Revision: https://phabricator.intern.facebook.com/D60251636

Summary: This adds support for vst{2,3,4}, which are not correctly handled by handleUnknownIntrinsic/handleVector{Load,Store}Intrinsic. This patch also updates the tests introduced in #98247 and #99555 --------- Co-authored-by: Vitaly Buka <vitalybuka@gmail.com> Test Plan: Reviewers: Subscribers: Tasks: Tags: Differential Revision: https://phabricator.intern.facebook.com/D60251436

[msan] Precommit MSan Arm NEON vst tests

2d65f14

These tests show that MSan currently does not handle vst (or vld) correctly.

thurstond requested review from vitalybuka and kstoimenov July 9, 2024 23:45

llvmbot added the clang Clang issues not falling into any other category label Jul 9, 2024

vitalybuka requested changes Jul 9, 2024

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thurstond added 2 commits July 16, 2024 16:56

Update test to use IR instead of C

3c00fe4

Update test comment

0c3c370

thurstond requested a review from vitalybuka July 16, 2024 18:15

thurstond added 2 commits July 16, 2024 19:42

Update test to use track-origins

665673c

Fix tool path

606fbe9

thurstond mentioned this pull request Jul 17, 2024

[msan] Implement support for Arm NEON vst{2,3,4} instructions #99360

Merged

Remove track-origins from test

6c771be

vitalybuka reviewed Jul 17, 2024

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thurstond merged commit ff08215 into llvm:main Jul 17, 2024
4 of 6 checks passed

sgundapa pushed a commit to sgundapa/upstream_effort that referenced this pull request Jul 23, 2024

[msan] Precommit MSan Arm NEON vst tests (llvm#98247)

4f8198c

These tests show that MSan currently does not handle vst (or vld) correctly.

thurstond mentioned this pull request Oct 30, 2024

MSAN reports false positives on interleaved storage on ARM AArch64 #72848

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[msan] Precommit MSan Arm NEON vst tests #98247

[msan] Precommit MSan Arm NEON vst tests #98247

thurstond commented Jul 9, 2024

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thurstond commented Jul 16, 2024

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[msan] Precommit MSan Arm NEON vst tests #98247

[msan] Precommit MSan Arm NEON vst tests #98247

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