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[aes] Hierarchical paths in AES RTL won't synthesize in DC #10180

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msfschaffner opened this issue Jan 19, 2022 · 10 comments · Fixed by #10202
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[aes] Hierarchical paths in AES RTL won't synthesize in DC #10180

msfschaffner opened this issue Jan 19, 2022 · 10 comments · Fixed by #10202

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@msfschaffner
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Hey @vogelpi - I just realized that we have added hierarchical paths in the AES RTL as part of the latest AES update:

assign a_gamma1_q = u_aes_dom_mul_gamma1_gamma0.gen_pipeline.a_x_q;
assign a_gamma0_q = u_aes_dom_mul_gamma1_gamma0.gen_pipeline.a_y_q;
assign b_gamma1_q = u_aes_dom_mul_gamma1_gamma0.gen_pipeline.b_x_q;
assign b_gamma0_q = u_aes_dom_mul_gamma1_gamma0.gen_pipeline.b_y_q;

This is not synthesizable and should only be used in TB code.
We need to fix this since otherwise DC errors out.

I can try and fix this tomorrow - but if anyone can take a look in the meantime that would be great.

@vogelpi
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vogelpi commented Jan 19, 2022

This syntax worked fine both in Yosys and Vivado. But I understand that it needs to be fixed. I'll have a look and for sure will have a PR ready by tomorrow morning. Sorry for causing this issue!

@vogelpi vogelpi self-assigned this Jan 19, 2022
vogelpi added a commit to vogelpi/opentitan that referenced this issue Jan 19, 2022
This resolves lowRISC#10180.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
@tjaychen
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tjaychen commented Jan 20, 2022 via email

msfschaffner added a commit to msfschaffner/opentitan that referenced this issue Jan 20, 2022
Fix lowRISC#10180

Signed-off-by: Michael Schaffner <msf@google.com>
@msfschaffner
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Hey I missed it as well ;).

I drafted a fix here: #10206

@vogelpi
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vogelpi commented Jan 20, 2022

This is kind of embarrassing: it turned out that Yosys also doesn't like the hierarchical reference. The resulting netlist (I've formally verified) was non functional :-(
On the new, correct netlist, formal masking verification takes much longer. At least we know that Vivado did the right thing (otherwise CI would have failed) and we also didn't see leakage in the FPGA experiments.

@vogelpi
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vogelpi commented Jan 20, 2022

Hey I missed it as well ;).

I drafted a fix here: #10206

Sorry Michael, I should have pinged you about the PR I did a couple of hours before yours: #10202

vogelpi added a commit to vogelpi/opentitan that referenced this issue Jan 20, 2022
This resolves lowRISC#10180.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
@tjaychen
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This is kind of embarrassing: it turned out that Yosys also doesn't like the hierarchical reference. The resulting netlist (I've formally verified) was non functional :-( On the new, correct netlist, formal masking verification takes much longer. At least we know that Vivado did the right thing (otherwise CI would have failed) and we also didn't see leakage in the FPGA experiments.

this is sort of a side topic. But does this mean we should file a bug on Yosys? If it actually doesn't like it, I feel like the flow should have error'd out instead of continuing to do something...weird.

msfschaffner pushed a commit that referenced this issue Jan 20, 2022
This resolves #10180.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
@msfschaffner
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Hey I missed it as well ;).
I drafted a fix here: #10206

Sorry Michael, I should have pinged you about the PR I did a couple of hours before yours: #10202

No worries, I closed my PR.

@msfschaffner
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This is kind of embarrassing: it turned out that Yosys also doesn't like the hierarchical reference. The resulting netlist (I've formally verified) was non functional :-( On the new, correct netlist, formal masking verification takes much longer. At least we know that Vivado did the right thing (otherwise CI would have failed) and we also didn't see leakage in the FPGA experiments.

this is sort of a side topic. But does this mean we should file a bug on Yosys? If it actually doesn't like it, I feel like the flow should have error'd out instead of continuing to do something...weird.

We probably should, yes. @vogelpi can you take care of this?

@vogelpi
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vogelpi commented Jan 21, 2022

After checking the sv2v output I can confirm it's a Yosys issue (and not our sv2v + Yosys flow). Checking the Yosys repository, it seems this is known (see YosysHQ/yosys#2266 and YosysHQ/yosys#647) and it produces at least warnings in the synthesis log:

syn_out/aes_sbox/generated/aes_sbox_dom.v:628: Warning: Identifier `\u_aes_dom_mul_gamma1_gamma0.gen_pipeline.a_x_q' is implicitly declared.
syn_out/aes_sbox/generated/aes_sbox_dom.v:629: Warning: Identifier `\u_aes_dom_mul_gamma1_gamma0.gen_pipeline.a_y_q' is implicitly declared.
syn_out/aes_sbox/generated/aes_sbox_dom.v:630: Warning: Identifier `\u_aes_dom_mul_gamma1_gamma0.gen_pipeline.b_x_q' is implicitly declared.
syn_out/aes_sbox/generated/aes_sbox_dom.v:631: Warning: Identifier `\u_aes_dom_mul_gamma1_gamma0.gen_pipeline.b_y_q' is implicitly declared.

The problem isn't easy to solve but @rswarbrick seems to have prepared a draft PR already that moves things in the right direction.

I will file a PR to our coding style guide to discourage usage of hierarchical references for code that is meant to be synthesized.

@tjaychen
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tjaychen commented Jan 21, 2022 via email

davidp135 pushed a commit to davidp135/opentitan that referenced this issue Feb 2, 2022
This resolves lowRISC#10180.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
luismarques pushed a commit to luismarques/opentitan that referenced this issue Feb 9, 2022
This resolves lowRISC#10180.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
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