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[dv,top_earlgrey] Fix pwrmgr_rstmgr_sva_if bind for top #24007

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merged 1 commit into from
Jul 18, 2024

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@matutem matutem commented Jul 12, 2024

The assertions pwrmgr_rstmgr_sva_if need to be disabled when either aon or main_pok are inactive. It is more reliable to bind them to rstmgr for top-level simulations. This PR does that and connects &rst_por_aon_n to rst_slow_ni, since rst_por_aon_n is 2-bit wide (one per domain), and captures the rstmgr behavior more accurately.

Fixes #23961

@matutem matutem marked this pull request as ready for review July 12, 2024 16:24
@matutem matutem requested a review from a team as a code owner July 12, 2024 16:25
@matutem matutem requested review from hcallahan-lowrisc and andreaskurth and removed request for a team July 12, 2024 16:25
@matutem matutem force-pushed the pwrmgr_main_power_glitch branch 6 times, most recently from 3d313cb to e44f7e9 Compare July 15, 2024 19:04
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LGTM except for one typo that seems to cause lint failures

name: "lowrisc:dv:rstmgr_unit_only_sva:0.1"
description: "RSTMGR assertion modules not suitable for chip level and bind file."
name: "lowrisc:dv:pwrmgr_unit_only_sva:0.1"
gdescription: "PWRMGR assertion interfaces not suitable for chip level bind file."
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gdescription is probably a typo?

Suggested change
gdescription: "PWRMGR assertion interfaces not suitable for chip level bind file."
description: "PWRMGR assertion interfaces not suitable for chip level bind file."

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This seems to cause the failure of the in-depth lint CI check

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Fixed, thanks.

The assertions pwrmgr_rstmgr_sva_if need to be disabled when either aon or
main_pok are inactive. It is more reliable to bind them to rstmgr for
top-level simulations. This PR does that and connects rst_slow_ni to
&rst_por_aon_n, since rst_por_aon_n is 2-bit wide (one per domain), and
captures the rstmgr behavior more accurately.

This also removes the rstmgr_unit_only* files for simplicity.

Fixes lowRISC#23961

Signed-off-by: Guillermo Maturana <maturana@opentitan.org>
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matutem commented Jul 18, 2024

The failures are unrelated. Merging this.

@matutem matutem merged commit 1a3d99a into lowRISC:master Jul 18, 2024
26 of 32 checks passed
@matutem matutem deleted the pwrmgr_main_power_glitch branch July 18, 2024 13:22
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[test-triage] chip_sw_pwrmgr_main_power_glitch_reset
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