GitHub - mahdizynali/verilog-digital-circuit-codes: simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)

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simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)

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Name		Name	Last commit message	Last commit date
Latest commit History 12 Commits
arithmaticUnit.v		arithmaticUnit.v
fullAdder.v		fullAdder.v
fullAdder_8bit.v		fullAdder_8bit.v
halfAdder.v		halfAdder.v
logicUnit.v		logicUnit.v
mux2to1.v		mux2to1.v
mux4to1.v		mux4to1.v
mux4to1_8bit.v		mux4to1_8bit.v
shiftLeftUnit.v		shiftLeftUnit.v
shiftRightUnit.v		shiftRightUnit.v