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Sep 16, 2025
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Update datasheets #119

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2c8ef7a
Update datasheets
jonnew Sep 16, 2025
193d7dc
fix typos/minor errors
cjsha Sep 16, 2025
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43 changes: 20 additions & 23 deletions source/Hardware Guide/Datasheets/bno055.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -99,38 +99,35 @@ All IMU data is signed with the exception of the calibration status bits (last
byte in the frame). The unit conversions for each of these measurements are as
follows:

- Euler angle (Tait-Bryan formalism)
Euler angle (Tait-Bryan formalism)
- Pitch: -180 to 180 degrees
- Roll: -90 to 90 degrees
- Yaw: 0 to 360 degrees

- Yaw: 0 to 360 degrees
- Roll: -180 to 180 degrees
- Pitch: -90 to 90 degrees
.. math::

.. math::
1^{\circ} = 16\ LSB

1^{\circ} = 16\ LSB
Quaternion
.. math::

- Quaternion
1 = 2^{14}\ LSB

.. math::
Acceleration & Gravity Vector
.. math::

1 = 2^{14}\ LSB
1\ m/s^2 = 100\ LSB

- Acceleration & Gravity Vector
Temperature
.. math::

.. math::
1^{\circ}C = 1\ LSB

1\ m/s^2 = 100\ LSB

- Temperature

.. math::

1^{\circ}C = 1\ LSB

- Calibration Status

- 0: not calibrated
- 3: fully calibrated
Calibration Status
- 0: Not calibrated
- 1: Poorly calibrated
- 2: Partially Calibrated
- 3: Fully calibrated

Host To Device Data Frames
******************************************
Expand Down
194 changes: 109 additions & 85 deletions source/Hardware Guide/Datasheets/fmc-digital-io.rst
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Expand Up @@ -2,8 +2,8 @@

FMC Host Digital IO Device
###########################################
:Authors: Jonathan P. Newman
:Version: 1
:Authors: Jonathan P. Newman, Aarón Cuevas López
:Version: 2
:IO: Frame Source, Frame Sink, Register Access
:ONIX ID: 18
:ONIX Hubs: :ref:`pcie_host`
Expand Down Expand Up @@ -46,26 +46,26 @@ The breakout to host serialization protocol is as follows:

|

Buttons
Buttons press state. Each bit represents the press state of a single
button in the 6-buttons bank.
Buttons
Buttons press state. Each bit represents the press state of a single
button in the 6-buttons bank.

- 0: Up
- 1: Down
- 0: Up
- 1: Down

Digital In
Digital input port. Each bit represents state of a signal line in the
8-bit port.
Digital In
Digital input port. Each bit represents state of a signal line in the
8-bit port.

- 0: Low
- 1: High
- 0: Low
- 1: High

Pnn
Headstage port power state. Each bit represents the power state of one of
the four headstage ports.
Pnn
Headstage port power state. Each bit represents the power state of one of
the four headstage ports.

- 0: Power off
- 1: Power on
- 0: Power off
- 1: Power on

A clock recovery circuit is required at the receiver to generate ``clk`` from
``sclk`` in order to sample the ``dat`` lines.
Expand Down Expand Up @@ -93,67 +93,67 @@ The host to breakout serialization protocol is as follows:

|

CMD
Two bit command word that determines what to do with SW.

- 0b00: Shift slow bits into slow shift register
- 0b01: Validate and move slow shift register to outputs and set initial
state to [0, ..., 0, slow1, slow0]. slow1 should be the desired MSB at
next command.
- 0b10: Reserved, same as 0b00 currently. Don't use.
- 0b11: Reset

SW
Two-bit "slow-word" part. These bits are accumulated over time in order
to control the display state and non-timing critical apsects of the
breakout board. For instance, LED colors and brightness, headstage lock
state, etc. As of this writing, for :ref:`breakout`, a complete
slow-word is as follows.

.. wavedrom::

{
reg: [
{bits: 1, name: "Acq. Running" },
{bits: 1, name: "Acq. Reset Done" },
{bits: 2, name: "Reserved" },
{bits: 4, name: "LED Level" },
{bits: 2, name: "LED Mode" },
{bits: 2, name: "Port A Status" },
{bits: 2, name: "Port B Status" },
{bits: 2, name: "Port C Status" },
{bits: 2, name: "Port D Status" },
{bits: 12, name: "Analog IO Dir." },
{bits: 2, name: "HARP Conf." },
{bits: 16, name: "GPIO Dir." }
],
config: {bits: 48, lanes: 8, vflip: true, hflip: true, fontsize: 11}
}

which are defined as follows:

- Acq. Running: Host hardware run state. 0 = not running, 1 = running
- Acq. Reset Done: Host reset state. 0 = reset not complete, 1 = reset
complete
- Reserved: NA
- LED Level: 4 bit register for general LED brighness. 0 = dimmest, 16 =
brightest
- LED Mode: 2 bit register for LED mode. 0 = all off, 1 = only
power/running, 2 = power/running, pll, harp, 3 = all on
- Port X Status: 2 bit register describing the headstage port state. 00:
power off, 01: power on, 10: locked, 11: device map good.
- Analog IO Dir.: 12 bit register describing the direcitonality of each
of the analog inputs. 0 = input, 1 = output.
- HARP Config.: 2 bit register for possible future harp configuration.
- GPIO Dir.: 16 bit register for possible future digital io
directionality configuration.

Digital Out
Digital output port state. Each bit represents state of an output signal
line in the 8-bit port.

- 0: Low
- 1: High
CMD
Two bit command word that determines what to do with SW.

- 0b00: Shift slow bits into slow shift register
- 0b01: Validate and move slow shift register to outputs and set initial
state to [0, ..., 0, slow1, slow0]. slow1 should be the desired MSB at
next command.
- 0b10: Reserved, same as 0b00 currently. Don't use.
- 0b11: Reset

SW
Two-bit "slow-word" part. These bits are accumulated over time in order
to control the display state and non-timing critical apsects of the
breakout board. For instance, LED colors and brightness, headstage lock
state, etc. As of this writing, for :ref:`breakout`, a complete
slow-word is as follows.

.. wavedrom::

{
reg: [
{bits: 1, name: "Acq. Running" },
{bits: 1, name: "Acq. Reset Done" },
{bits: 2, name: "Reserved" },
{bits: 4, name: "LED Level" },
{bits: 2, name: "LED Mode" },
{bits: 2, name: "Port A Status" },
{bits: 2, name: "Port B Status" },
{bits: 2, name: "Port C Status" },
{bits: 2, name: "Port D Status" },
{bits: 12, name: "Analog IO Dir." },
{bits: 2, name: "HARP Conf." },
{bits: 16, name: "GPIO Dir." }
],
config: {bits: 48, lanes: 8, vflip: true, hflip: true, fontsize: 11}
}

which are defined as follows:

- Acq. Running: Host hardware run state. 0 = not running, 1 = running
- Acq. Reset Done: Host reset state. 0 = reset not complete, 1 = reset
complete
- Reserved: NA
- LED Level: 4 bit register for general LED brighness. 0 = dimmest, 16 =
brightest
- LED Mode: 2 bit register for LED mode. 0 = all off, 1 = only
power/running, 2 = power/running, pll, harp, 3 = all on
- Port X Status: 2 bit register describing the headstage port state. 00:
power off, 01: power on, 10: locked, 11: device map good.
- Analog IO Dir.: 12 bit register describing the direcitonality of each
of the analog inputs. 0 = input, 1 = output.
- HARP Config.: 2 bit register for possible future harp configuration.
- GPIO Dir.: 16 bit register for possible future digital io
directionality configuration.

Digital Out
Digital output port state. Each bit represents state of an output signal
line in the 8-bit port.

- 0: Low
- 1: High

A clock recovery circuit is required at the receiver to generate ``clk`` from
``sclk`` in order to sample the ``dat`` line.
Expand Down Expand Up @@ -203,9 +203,9 @@ Register Programming
- LEDLVL
- R/W
- On Reset
- 0x0007
- 0x0003
- None
- The four LSBs dertermine the overall LED brightness. Brightness
- The four LSBs determine the overall LED brightness. Brightness
increases linearly with this register's 0-15 value.

* - 0x03
Expand All @@ -222,7 +222,33 @@ Register Programming
- On Reset
- 0x0000
- None
- GPIO configuraiton. Reserved for future use.
- GPIO configuration. Reserved for future use.

* - 0x05
- CLKHZ
- R
- N/A
- N/A
- None
- The system clock frequency in Hz

* - 0x06
- SPACING
- R/W
- On Reset
- 0x0000
- None
- Minimum CLK_HZ cycles between samples. Can be used to debounce inputs.
Ignored if SAMPLING > 0.

* - 0x07
- SAMPLING
- R/W
- On Reset
- 0x0000
- None
- If > 0, produce one sample with each SAMPLING value of the CLK_HZ clock.
regardless of if there are changes in digital input state or not.

.. _onidatasheet_fmc_digital_io_d2h:

Expand Down Expand Up @@ -254,8 +280,6 @@ current digital input and user input state.
config: {bits: 224, lanes: 7, vflip: true, hflip: true, fontsize: 11}
}

|

Input Port State
8-bit input port state

Expand Down Expand Up @@ -287,5 +311,5 @@ output port state:

|

Output Port State
8-bit output port state
Output Port State
8-bit output port state
36 changes: 18 additions & 18 deletions source/Hardware Guide/Datasheets/fmc-link-control.rst
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Expand Up @@ -109,7 +109,7 @@ Register Programming
- R
- When LOCK or PASS change
- 0
- None
- None
- Link state

* Bit 0: LOCK
Expand All @@ -123,7 +123,7 @@ Register Programming
- None
- Misc. options for the link device

* Bit 0: `0` Port auto-shutdown disabled `1` Port auto-shutdown enabled
* Bit 0: `0` Port auto-shutdown disabled `1` Port auto-shutdown enabled

.. _onidatasheet_fmc_link_control_d2h:

Expand Down Expand Up @@ -158,28 +158,28 @@ Each frame transmitted to the host is structured as follows:
This device produces frames when triggered by the **CV**, **PP**, or **SL**
bits. These are defined as follows:

CV
Codeword valid. Indicates that the Status Codeword field has valid data.
A frame is produced when this bit goes high. The codeword meaning is
hub-dependent. See hub documentation for definitions.
CV
Codeword valid. Indicates that the Status Codeword field has valid data.
A frame is produced when this bit goes high. The codeword meaning is
hub-dependent. See hub documentation for definitions.

PP
Parity check pass. This bit reflects the state of the PASS pin on the
DS90UB9x4 deserializer.
PP
Parity check pass. This bit reflects the state of the PASS pin on the
DS90UB9x4 deserializer.

- 0b0: One or more errors were detected in the received payload.
- 0b1: Error free transmission in forward channel operation.
- 0b0: One or more errors were detected in the received payload.
- 0b1: Error free transmission in forward channel operation.

A frame is produced whenever this bit changes state.
A frame is produced whenever this bit changes state.

SL
SERDES lock. This bit reflects the state of the LOCK pin on the DS90UB9x4
deserializer, which monitors the lock status of FPD-Link III channel.
SL
SERDES lock. This bit reflects the state of the LOCK pin on the DS90UB9x4
deserializer, which monitors the lock status of FPD-Link III channel.

- 0b0: PLL is unlocked link is down.
- 0b1: PLL is locked, link is active.
- 0b0: PLL is unlocked link is down.
- 0b1: PLL is locked, link is active.

A frame is produced whenever this bit changes state.
A frame is produced whenever this bit changes state.

Host To Device Data Frames
******************************************
Expand Down
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