OpenCompact v0.3.0

OpenCompact v0.3.0

A minor release of OpenCompact, the CCSDS 123.0-B-2 hyperspectral and multispectral image compression core, at
technology readiness level 3 (fully verified by simulation; not tested on hardware, no flight heritage). It is the
version of the first hardware test of a reference system of the family (spfi_compress), the path to TRL 4.

Changes since v0.2.0

• Added: runtime parameters (RuntimeParams_g, default false, only with RuntimeConfig_g). Every image takes its
  own user-defined data, sub-frame interleaving depth M (BI order), weight update parameters (log2 t_inc, vmin, vmax)
  and entropy coder parameters (Umax, gamma0, gamma* and K of the sample-adaptive coder; Umax, gamma0 and gamma* of
  the hybrid coder; r of the block-adaptive coder). They come from new ports of ocp_core (Cfg_UserData to
  Cfg_RefInterval, Act_UserData to Act_RefInterval) or, in ocp_channel, from new AXI4-Lite registers of
  ocp_mib (NEXT_SAMPLES, NEXT_ORDER, NEXT_WEIGHTS, NEXT_ADAPTIVE, NEXT_BLOCK) committed with the dimensions. The
  header of every image carries its parameters. With the generic false the compressed images, the throughput and the
  registers of the GHDL netlist are those of v0.2.0. User guide section 4.5.
• Added: register map version 3 (ID 0x4F435003): NEXT_SAMPLES to NEXT_BLOCK and GENERICS.RUNTIME_PARAMS; the
  existing registers keep their offsets and fields.
• Added: a decoder in the reference model (ocp_model.decompress, tools/ocp_decompress.py, user guide section
  11). It decodes a compressed image of any configuration of CCSDS 123.0-B-2 in Python, without other software, and
  reconstructs what the CNES reference decoder reconstructs. It is the decompression step of the hardware test of a
  reference system.
• Added: lint/xsim_smoke.py also elaborates and simulates the runtime parameter configurations (167 top levels).

Designs using v0.2.0 need no change: the new generic defaults to the previous behaviour, the new ports have defaults or
are unused with it, and the register map only adds registers.

Verification

• The RTL of the release (hdl/*/src) and the Open Logic pin equal those of commit 8be9d95. The full QuestaSim
  regression and the CCSDS test data set ran on that commit. The commits after it add the decoder of the reference
  model (tools), tests from the coverage review, and documentation.
• QuestaSim (Questa Pro Microchip Edition 2024.3, time resolution 1 fs): 613 tests, all passing in the optimised run
  without code coverage and with code coverage. 607 of them ran on 8be9d95. The 6 tests added by the coverage review,
  and the MIB test they extend, ran on the same RTL with the added tests.
• Code coverage: statements 2388 / 2408 (99.2 %), branches 1076 / 1088 (98.9 %), conditions 224 / 254 (88.2 %),
  expressions 224 / 248 (90.3 %); every state of the state machines, and every transition except the recovery
  transition of the image-start sequencer. Every remaining miss is justified in docs/coverage.md.
• GHDL 6.0.0: the full regression in the CI of the release, 613 of 613 tests.
• CCSDS test data selection: 1275 of 1275 tests pass in GHDL.
• AMD Vivado simulator 2025.2: 167 of 167 top levels of lint/xsim_smoke.py elaborate and run without an error.
• Mutations of the runtime parameters: 54 of 54 make their test fail (51 of the first version, 3 for the paths found
  by the coverage review).
• Decoder of the reference model:
  • all 6474 images of the CCSDS test data set decode correctly: the 4908 lossless ones exactly, the 1566
    near-lossless ones within the maximum error of every sample;
  • all 1566 near-lossless images decode bit for bit as with the CNES reference decoder;
  • 90 tests in the CI (python -m pytest tools/tests).
• VSG, markdownlint, compliance matrix and register map checks are clean.

Dependencies

• Open Logic 4.7.0-ft.9 (open-space-hdl/open-logic-ft, submodule open-logic).
• VHDL-2008; verified with GHDL 6.0.0, QuestaSim 2024.3 and the AMD Vivado simulator 2025.2. The decoder needs Python
  3 only.

Known issues and open items

• With RuntimeParams_g false the GHDL netlist keeps the registers of v0.2.0, and with RuntimeConfig_g false those
  of v0.1.1. The equal utilisation after FPGA synthesis is still to be confirmed with the out-of-context Vivado flow
  (lint/vivado_ooc.py, core verification report, section 5).
• TRL 4 needs the hardware test of a reference system that contains the core (roadmap).