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Update the interrupt vector table in the documentation #273

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DanieleParravicini-Synthara

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@@ -4,17 +4,18 @@ Exceptions and Interrupts
=========================

Ibex implements trap handling for interrupts and exceptions according to the RISC-V Privileged Specification, version 1.11.
(Is it fully compatible with `RISC-V Privileged Specification, version 1.12 <https://drive.google.com/file/d/1EMip5dZlnypTk7pt4WWUKmtjUKTOkBqh/view>`?).
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There is always some confusion about version of RISC-V specs, but I do not believe this is correct. According to the CV32E20 Specification (not to be confused with this User Manual), the target privileged specification for the CV32E20 is The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 20211203, which I believe is v.1.13.

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I would gladly put a reference to the correct instruction set manual if you point me to the correct version

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The spec for the above version of the priv spec has been added to the RISC-V Technical Specifications Archive (link).

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I see, the CV32E20 specification points to The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 20211203, but there I couldn't find something that said the version v1.xy .
For now I will put the reference to the link you provided

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updated

@MikeOpenHWGroup
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Hi @DanieleParravicini-Synthara. I recommend that we have a (virtual) in-person discussion with @davideschiavone and @MarioOpenHWGroup before we proceed much future with this PR. In the meantime, you will need to be covered by the Eclipse Contributor Agreement before any PRs from you can be accepted. As Synthara is an OpenHW Group member, it is best for you to use a GitHub repo associated with your employer, rather than a person account.

@DanieleParravicini
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Will change the signature

Removes the reference to the boot_addr_i+0x80
that was coming from legacy documentation and substitute with
boot_addr_i where necessary.
Adds a tentative description of the interrupt vector table.
That has to be reviewed and adjusted.
@DanieleParravicini-Synthara
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Hello @MikeOpenHWGroup, I changed the signature of all the commits.
Sure, MaurizioCapra( the guy in charge of RISC-V development in synthara ) and I would be available for a call

@DanieleParravicini-Synthara
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In the meanwhile I will ask to complete the ECA

@MikeOpenHWGroup
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In the meanwhile I will ask to complete the ECA

Hi @DanieleParravicini. I see that you are now properly covered by the ECA using your Synthara credentials. However, there are still at least two commits in this PR from non-Synthata credentials and these will block the merge. You have two options:

  1. Rebase the commits on this PR.
  2. Close this PR and submit a fresh one from your Synthara credentials.

@DanieleParravicini-Synthara
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Hey @MikeOpenHWGroup, sorry for the mistake.

They should be rebased now

@DanieleParravicini-Synthara
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The PR itself is not much but I hope it can help

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@DanieleParravicini-Synthara
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So you think that I got this right?

@DanieleParravicini-Synthara DanieleParravicini-Synthara marked this pull request as ready for review June 13, 2024 14:16
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4 participants