8368732: RISC-V: Detect support for misaligned vector access via hwprobe

src/hotspot/cpu/riscv/vm_version_riscv.cpp

@@ -160,7 +160,7 @@ void VM_Version::common_initialize() {
 
   if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
     FLAG_SET_DEFAULT(AvoidUnalignedAccesses,
-      unaligned_access.value() != MISALIGNED_FAST);
+      unaligned_scalar.value() != MISALIGNED_SCALAR_FAST);
   }
 
   if (!AvoidUnalignedAccesses) {
@@ -175,7 +175,12 @@ void VM_Version::common_initialize() {
   // This machine has fast unaligned memory accesses
   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
     FLAG_SET_DEFAULT(UseUnalignedAccesses,
-      unaligned_access.value() == MISALIGNED_FAST);
+      (unaligned_scalar.value() == MISALIGNED_SCALAR_FAST));
+  }
+
+  if (FLAG_IS_DEFAULT(AlignVector)) {
+    FLAG_SET_DEFAULT(AlignVector,
+      unaligned_vector.value() != MISALIGNED_VECTOR_FAST);
   }
 
 #ifdef __riscv_ztso

src/hotspot/cpu/riscv/vm_version_riscv.hpp

@@ -227,7 +227,8 @@ class VM_Version : public Abstract_VM_Version {
   // mvendorid Manufactory JEDEC id encoded, ISA vol 2 3.1.2..
   // marchid   Id for microarch. Mvendorid plus marchid uniquely identify the microarch.
   // mimpid    A unique encoding of the version of the processor implementation.
-  // unaligned_access Unaligned memory accesses (unknown, unspported, emulated, slow, firmware, fast)
+  // unaligned_scalar Performance of misaligned scalar accesses (unknown, emulated, slow, fast, unsupported)
+  // unaligned_vector Performance of misaligned vector accesses (unknown, unspported, slow, fast)
   // satp mode SATP bits (number of virtual addr bits) mbare, sv39, sv48, sv57, sv64
 
  public:
@@ -287,11 +288,12 @@ class VM_Version : public Abstract_VM_Version {
   // Non-extension features
   //
   #define RV_NON_EXT_FEATURE_FLAGS(decl)                                                       \
-  decl(unaligned_access ,  Unaligned       ,  RV_NO_FLAG_BIT,  false,  NO_UPDATE_DEFAULT)      \
   decl(mvendorid        ,  VendorId        ,  RV_NO_FLAG_BIT,  false,  NO_UPDATE_DEFAULT)      \
   decl(marchid          ,  ArchId          ,  RV_NO_FLAG_BIT,  false,  NO_UPDATE_DEFAULT)      \
   decl(mimpid           ,  ImpId           ,  RV_NO_FLAG_BIT,  false,  NO_UPDATE_DEFAULT)      \
   decl(satp_mode        ,  SATP            ,  RV_NO_FLAG_BIT,  false,  NO_UPDATE_DEFAULT)      \
+  decl(unaligned_scalar ,  UnalignedScalar ,  RV_NO_FLAG_BIT,  false,  NO_UPDATE_DEFAULT)      \
+  decl(unaligned_vector ,  UnalignedVector ,  RV_NO_FLAG_BIT,  false,  NO_UPDATE_DEFAULT)      \
   decl(zicboz_block_size,  ZicbozBlockSize ,  RV_NO_FLAG_BIT,  false,  NO_UPDATE_DEFAULT)      \
 
   #define DECLARE_RV_NON_EXT_FEATURE(NAME, PRETTY, LINUX_BIT, FSTRING, FLAGF)      \
@@ -432,12 +434,19 @@ class VM_Version : public Abstract_VM_Version {
   static VM_MODE parse_satp_mode(const char* vm_mode);
 
   // Values from riscv_hwprobe()
-  enum UNALIGNED_ACCESS : int {
-    MISALIGNED_UNKNOWN     = 0,
-    MISALIGNED_EMULATED    = 1,
-    MISALIGNED_SLOW        = 2,
-    MISALIGNED_FAST        = 3,
-    MISALIGNED_UNSUPPORTED = 4
+  enum UNALIGNED_SCALAR_ACCESS : int {
+    MISALIGNED_SCALAR_UNKNOWN     = 0,
+    MISALIGNED_SCALAR_EMULATED    = 1,
+    MISALIGNED_SCALAR_SLOW        = 2,
+    MISALIGNED_SCALAR_FAST        = 3,
+    MISALIGNED_SCALAR_UNSUPPORTED = 4
+  };
+
+  enum UNALIGNED_VECTOR_ACCESS : int {
+    MISALIGNED_VECTOR_UNKNOWN     = 0,
+    MISALIGNED_VECTOR_SLOW        = 2,
+    MISALIGNED_VECTOR_FAST        = 3,
+    MISALIGNED_VECTOR_UNSUPPORTED = 4
   };
 
   // Null terminated list

src/hotspot/os_cpu/linux_riscv/riscv_hwprobe.cpp

@@ -89,7 +89,24 @@
 #define   RISCV_HWPROBE_MISALIGNED_UNSUPPORTED  (4 << 0)
 #define   RISCV_HWPROBE_MISALIGNED_MASK         (7 << 0)
 
-#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
+#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE      6
+
+#define RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS   7
+
+#define RISCV_HWPROBE_KEY_TIME_CSR_FREQ          8
+
+#define RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF 9
+#define   RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN       0
+#define   RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED      1
+#define   RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW          2
+#define   RISCV_HWPROBE_MISALIGNED_SCALAR_FAST          3
+#define   RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED   4
+
+#define RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF 10
+#define   RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN       0
+#define   RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW          2
+#define   RISCV_HWPROBE_MISALIGNED_VECTOR_FAST          3
+#define   RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED   4
 
 #ifndef NR_riscv_hwprobe
 #ifndef NR_arch_specific_syscall
@@ -117,7 +134,11 @@ static struct riscv_hwprobe query[] = {{RISCV_HWPROBE_KEY_MVENDORID, 0},
                                        {RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0},
                                        {RISCV_HWPROBE_KEY_IMA_EXT_0,     0},
                                        {RISCV_HWPROBE_KEY_CPUPERF_0,     0},
-                                       {RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE, 0}};
+                                       {RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE,      0},
+                                       {RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS,   0},
+                                       {RISCV_HWPROBE_KEY_TIME_CSR_FREQ,          0},
+                                       {RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF, 0},
+                                       {RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF, 0}};
 
 bool RiscvHwprobe::probe_features() {
   assert(!rw_hwprobe_completed, "Called twice.");
@@ -246,9 +267,20 @@ void RiscvHwprobe::add_features_from_query_result() {
     VM_Version::ext_Zicond.enable_feature();
   }
 #endif
+  // RISCV_HWPROBE_KEY_CPUPERF_0 is deprecated and returns similar values
+  // to RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF. Keep it there for backward
+  // compatibility with old kernels.
   if (is_valid(RISCV_HWPROBE_KEY_CPUPERF_0)) {
-    VM_Version::unaligned_access.enable_feature(
+    VM_Version::unaligned_scalar.enable_feature(
        query[RISCV_HWPROBE_KEY_CPUPERF_0].value & RISCV_HWPROBE_MISALIGNED_MASK);
+  } else if (is_valid(RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF)) {
+    VM_Version::unaligned_scalar.enable_feature(
+       query[RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF].value);
+  }
+
+  if (is_valid(RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF)) {
+    VM_Version::unaligned_vector.enable_feature(
+       query[RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF].value);
   }
   if (is_valid(RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE)) {
     VM_Version::zicboz_block_size.enable_feature(query[RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE].value);

src/hotspot/os_cpu/linux_riscv/vm_version_linux_riscv.cpp

@@ -303,7 +303,7 @@ void VM_Version::rivos_features() {
 
   ext_Zvfh.enable_feature();
 
-  unaligned_access.enable_feature(MISALIGNED_FAST);
+  unaligned_scalar.enable_feature(MISALIGNED_SCALAR_FAST);
   satp_mode.enable_feature(VM_SV48);
 
   // Features dependent on march/mimpid.