WIP: Add AXI DMA backend #110
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WRoenninger
requested changes
May 18, 2020
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Thank you Thomas for this valuable contribution to the AXI infrastructure.
Overall I think this is a really good architecture for a high performance AXI DMA backend.
- I added some suggestions to bring the parameterization in line with the Styleguide.
The suggestions are general and should be done on all parameters/constants. - There are some instances where I think that the design intend would be clearer if some additional typedefs are used. (
axi_dam_data_path) - I think it would be a good idea to add some assertions where wrong stearing of the backend leads to unexpected behavior.
| // top level of the simulation for the AXI DMA backend | ||
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| `timescale 1ns/1ns | ||
| module tb_axi_dma_backend; |
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Some sort of comment on what the idea with the testbench / fixture construct is would be nice.
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| // Copyright (c) 2019 ETH Zurich, University of Bologna | ||
| // All rights reserved. | ||
| // | ||
| // This code is under development and not yet released to the public. | ||
| // Until it is released, the code is under the copyright of ETH Zurich and | ||
| // the University of Bologna, and may contain confidential and/or unpublished | ||
| // work. Any reuse/redistribution is strictly forbidden without written | ||
| // permission from ETH Zurich. | ||
| // | ||
| // Thomas Benz <tbenz@ethz.ch> |
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I am closing this PR, as agreed with @thommythomaso, to focus work on integrating the successor version as soon as possible. This state will remain available under the tag |
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AXI DMA backend can execute arbitrary 1D data movement operations on an AXI4 bus.
This PR includes:
and the test infrastructure:
The interface of the backend is documented with inline docstrings. An additional architectural description including block diagrams will be supplied later.