Skip to content
AXI4 and AXI4-Lite interface definitions and testbench utilities
SystemVerilog Stata Shell
Branch: master
Clone or download
Latest commit d252bdf Aug 9, 2019
Type Name Latest commit message Commit time
Failed to load latest commit information.
include/axi assign.svh: Add trailing semicolon to `AXI_ASSIGN()` and `AXI_LITE_AS… Feb 26, 2019
scripts scripts: Update to `bender script` Aug 8, 2019
test test/synth_bench: Update modports May 24, 2019
.gitignore Add bender file Feb 16, 2018
.gitlab-ci.yml 💚 Fix CI run Mar 6, 2018
Bender.yml Bender: Update author list May 28, 2019 Changelog: Add v0.7.0 May 28, 2019
LICENSE Replace non-ASCII characters in Solderpad license text Feb 26, 2019
src_files.yml Add AXI ATOP filter Feb 22, 2019


This is the implementation of the AMBA AXI protocol developed as part of the PULP platform as ETH Zurich. This repository will eventually contain interface definitions, crossbars, data width converters, traffic generators, and testbench utilities.

We implement AXI4+ATOPs and AXI4-Lite.

AXI4+ATOPs means the full AXI4 specification plus atomic operations (ATOPs) as defined in Section E2.1 of the AMBA5 specification. This has the following implications for modules that do not implement ATOPs and systems that include such modules:

  • Masters that do not issue ATOPs can simply permanently set aw_atop to 0.
  • Slaves that do not support ATOPs must specify this in their interface documentation and can ignore the aw_atop signal.
  • System designers are responsible for ensuring that slaves that do not support ATOPs are behind an axi_atop_filter if any master could issue an ATOP to such slaves.

Masters and slaves that do support ATOPs must adhere to Section E2.1 of the AMBA5 specification.

You can’t perform that action at this time.