Integrate Culsans on top of Astral modifications.

.gitmodules

@@ -6,3 +6,7 @@
 	path = sw/deps/cva6-sdk
 	url = https://github.com/pulp-platform/cva6-sdk.git
 	ignore = dirty
+[submodule "sw/deps/rv_iommu_tests"]
+	path = sw/deps/rv_iommu_tests
+	url = https://github.com/zero-day-labs/riscv-iommu-tests.git
+	branch = pulp

Bender.lock

@@ -1,4 +1,11 @@
 packages:
+  ace:
+    revision: ea2fc9ced5be964b47cfcbcd6eb6518771a9e85d
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/ace.git
+    dependencies:
+    - axi
   apb:
     revision: 77ddf073f194d44b9119949d2421be59789e69ae
     version: 0.2.4
@@ -15,23 +22,24 @@ packages:
     - apb
     - register_interface
   axi:
-    revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6
-    version: 0.39.3
+    revision: 587355b77b8ce94dcd600efbd5d5bd118ff913a7
+    version: 0.39.4
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
     - common_cells
     - common_verification
     - tech_cells_generic
   axi_llc:
-    revision: 4deb8c6281c74b3882846ad933f42a8c6568cbe0
+    revision: 2f23e6fc40ac7256f177a44c1f106c70c05c6cca
     version: null
     source:
       Git: https://github.com/pulp-platform/axi_llc
     dependencies:
     - axi
     - common_cells
     - common_verification
+    - redundancy_cells
     - register_interface
     - tech_cells_generic
   axi_riscv_atomics:
@@ -44,8 +52,8 @@ packages:
     - common_cells
     - common_verification
   axi_rt:
-    revision: 56074a195b1c8b05f4bdd73674e437bbcb35f2cd
-    version: 0.0.0-alpha.7
+    revision: d5f857e74d0a5db4e4a2cc3652ca4f40f29a1484
+    version: 0.0.0-alpha.8
     source:
       Git: https://github.com/pulp-platform/axi_rt.git
     dependencies:
@@ -85,8 +93,8 @@ packages:
     - common_cells
     - register_interface
   common_cells:
-    revision: f4d6406070d8e7767e4e9a433f11b039859f03a1
-    version: null
+    revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb
+    version: 1.37.0
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
@@ -99,11 +107,12 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   cva6:
-    revision: 2f0d702b58a07827d93ac13a3eed815b76ea4ffc
+    revision: 125c68eeb1a64c20db652be15491c19e03730b70
     version: null
     source:
       Git: https://github.com/pulp-platform/cva6.git
     dependencies:
+    - ace
     - axi
     - common_cells
     - fpnew
@@ -125,8 +134,8 @@ packages:
     dependencies:
     - common_cells
   idma:
-    revision: 95f366e56f7e772c283fb3c8b343afc4a3978375
-    version: 0.6.2
+    revision: c12caf59bb482fe44b27361f6924ad346b2d22fe
+    version: 0.6.3
     source:
       Git: https://github.com/pulp-platform/iDMA.git
     dependencies:
@@ -146,8 +155,8 @@ packages:
     - common_cells
     - register_interface
   obi:
-    revision: 1aa411df145c4ebdd61f8fed4d003c33f7b20636
-    version: 0.1.2
+    revision: 5321106817e177d6c16ecc4daa922b96b1bc946b
+    version: 0.1.5
     source:
       Git: https://github.com/pulp-platform/obi.git
     dependencies:
@@ -163,7 +172,7 @@ packages:
     - register_interface
     - tech_cells_generic
   redundancy_cells:
-    revision: c44ff73521186d2bc1dd77a17664539a3b3e2406
+    revision: 9e31f7c6c24877eaf58279903e7a162b16c9a721
     version: null
     source:
       Git: https://github.com/pulp-platform/redundancy_cells.git
@@ -190,6 +199,15 @@ packages:
     dependencies:
     - common_cells
     - tech_cells_generic
+  riscv-iommu:
+    revision: c1dea3732d0d05e5659b31773e43f3364bc866fc
+    version: null
+    source:
+      Git: https://github.com/zero-day-labs/riscv-iommu.git
+    dependencies:
+    - axi
+    - common_cells
+    - register_interface
   serial_link:
     revision: 5a25f5a71074f1ebb6de7b5280f2b16924bcc666
     version: 1.1.1

Bender.yml

@@ -13,25 +13,27 @@ package:
 
 dependencies:
   apb_uart:                 { git: "https://github.com/pulp-platform/apb_uart.git",               version: 0.2.1  }
-  axi:                      { git: "https://github.com/pulp-platform/axi.git",                    version: 0.39.2 }
-  axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc",                    rev: 4deb8c6    } # branch: astral
+  ace:                      { git: "https://github.com/pulp-platform/ace.git",                    rev: ea2fc9ced5be964b47cfcbcd6eb6518771a9e85d } # branch: ace-cut
+  axi:                      { git: "https://github.com/pulp-platform/axi.git",                    version: 0.39.4 }
+  axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc",                    rev: 2f23e6f    } # branch: rt/fix-no-ecc-config
   axi_riscv_atomics:        { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",      rev: 034bf8941  } # branch: master
-  axi_rt:                   { git: "https://github.com/pulp-platform/axi_rt.git",                 version: 0.0.0-alpha.7 }
+  axi_rt:                   { git: "https://github.com/pulp-platform/axi_rt.git",                 version: 0.0.0-alpha.8 }
   axi_vga:                  { git: "https://github.com/pulp-platform/axi_vga.git",                version: 0.1.3  }
   clic:                     { git: "https://github.com/pulp-platform/clic.git",                   rev: 40ae266    } # branch: critical-path
   clint:                    { git: "https://github.com/pulp-platform/clint.git",                  version: 0.2.0  }
-  common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           rev: f4d6406070 } # branch: master
+  common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           version: 1.37.0 }
   common_verification:      { git: "https://github.com/pulp-platform/common_verification.git",    version: 0.2.0  }
-  cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: "2f0d702"  } # branch: astral-pulp-v1
+  cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: 125c68e    } # branch: rt/astral-culsans/add-aw-lock
   iDMA:                     { git: "https://github.com/pulp-platform/iDMA.git",                   version: 0.6.2  }
   irq_router:               { git: "https://github.com/pulp-platform/irq_router.git",             version: 0.0.1-beta.1 }
   opentitan_peripherals:    { git: "https://github.com/pulp-platform/opentitan_peripherals.git",  version: 0.4.0  }
-  redundancy_cells:         { git: "https://github.com/pulp-platform/redundancy_cells.git",       rev: "c44ff735" } # branch: astral-v0
+  redundancy_cells:         { git: "https://github.com/pulp-platform/redundancy_cells.git",       rev: 9e31f7c    } # branch: astral-v0
   register_interface:       { git: "https://github.com/pulp-platform/register_interface.git",     version: 0.4.4  }
   riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              version: 0.8.1  }
   serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.1  }
   tagger:                   { git: "https://github.com/pulp-platform/transaction-tagger.git",     rev: b288376    }
   unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.6  }
+  riscv-iommu:              { git: "https://github.com/zero-day-labs/riscv-iommu.git",            rev: 26ae5a844  } # branch: pulp
 
 export_include_dirs:
   - hw/include

cheshire.mk

@@ -8,7 +8,7 @@
 
 BENDER ?= bender
 
-VLOG_ARGS ?= -suppress 2583 -suppress 13314
+VLOG_ARGS ?= -suppress 2583 -suppress 13314 -suppress 13276
 VSIM      ?= vsim
 
 MAXPARTITION 	?= 16
@@ -40,7 +40,7 @@ BENDER_ROOT ?= $(CHS_ROOT)/.bender
 # Ensure both Bender dependencies and (essential) submodules are checked out
 $(BENDER_ROOT)/.chs_deps:
 	$(BENDER) checkout
-	cd $(CHS_ROOT) && git submodule update --init --recursive sw/deps/printf
+	cd $(CHS_ROOT) && git submodule update --init --recursive sw/deps/printf sw/deps/rv_iommu_tests
 	@touch $@
 
 # Make sure dependencies are more up-to-date than any targets run
@@ -58,7 +58,7 @@ chs-clean-deps:
 ######################
 
 CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git
-CHS_NONFREE_COMMIT ?= d0a0c9a # branch: astral
+CHS_NONFREE_COMMIT ?= 017cd2f9 # branch: astral
 
 chs-nonfree-init:
 	git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree
@@ -81,7 +81,7 @@ $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv:
 	$(REGTOOL) -r $< --outdir $(dir $@)
 
 # CLINT
-CLINTCORES ?= 1
+CLINTCORES ?= 2
 include $(CLINTROOT)/clint.mk
 $(CLINTROOT)/.generated:
 	flock -x $@ $(MAKE) clint && touch $@
@@ -153,8 +153,10 @@ CHS_BOOTROM_ALL += $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv $(CHS_ROOT)/hw/boo
 # Simulation #
 ##############
 
-$(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: $(CHS_ROOT)/Bender.yml
-	$(BENDER) script vsim -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 -t rtl -t snitch_cluster --vlog-arg="$(VLOG_ARGS)" > $@
+CVA6_TARGET ?= cv64a6_imafdc_sv39_wb # cv64a6_imafdcsclic_sv39
+
+$(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: Bender.yml
+	$(BENDER) script vsim -t sim -t $(CVA6_TARGET) -t test -t cva6 -t rtl -t snitch_cluster --vlog-arg="$(VLOG_ARGS)" > $@
 	echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@
 
 .PRECIOUS: $(CHS_ROOT)/target/sim/models

hw/bootrom/cheshire_bootrom.S

@@ -5,10 +5,15 @@
 // Nicole Narr <narrn@student.ethz.ch>
 // Christopher Reinwardt <creinwar@student.ethz.ch>
 // Paul Scheffler <paulsc@iis.ee.ethz.ch>
+// Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
 
-// TODO: Avoid hardcoding in addresses and offsets
+#include <regs/cheshire.h>
+#include <regs/axi_llc.h>
 
-#include "smp.h"
+// The hart that non-SMP tests should run on
+#ifndef NONSMP_HART
+#define NONSMP_HART 0
+#endif
 
 .section .text._start
 
@@ -47,7 +52,11 @@ _start:
     li x31, 0
 
     // Pause SMP harts
-    smp_pause(t0, t1)
+    li   t1, 0x8
+    csrw mie, t1
+    li   t0, NONSMP_HART
+    csrr t1, mhartid
+    bne  t0, t1, _wait_for_ipi
 
     // Init stack and global pointer with safe, linked values
     la sp, __stack_pointer$
@@ -57,57 +66,102 @@ _start:
     .option pop
 
     // If LLC present: Wait for end of BIST, then extend stack and set to all SPM
-    la t0, __base_regs
-    lw t0, 80(t0)   // regs.HW_FEATURES
-    andi t0, t0, 2  // regs.HW_FEATURES.llc
+    la   t0, __base_regs
+    lw   t0, CHESHIRE_HW_FEATURES_REG_OFFSET(t0)
+    andi t0, t0, 2  // HW_FEATURES.llc
     beqz t0, _prom_check_run
     la t0, __base_llc
     // Only configure half of LLC as SPM
 _wait_llc_bist:
-    lw t1, 72(t0)   // llc.BIST_STATUS_DONE_BIT
+    lw   t1, AXI_LLC_BIST_STATUS_REG_OFFSET(t0) // Check BIST status done bit
     beqz t1, _wait_llc_bist
-    li t1, -1
-    sw t1, 0(t0)    // llc.CFG_SPM_LOW
-    sw t1, 4(t0)    // llc.CFG_SPM_HIGH
-    li t1, 1
-    sw t1, 16(t0)   // llc.CFG_COMMIT
+    li   t1, -1
+    sw   t1, AXI_LLC_CFG_SPM_LOW_REG_OFFSET(t0)
+    sw   t1, AXI_LLC_CFG_SPM_HIGH_REG_OFFSET(t0)
+    li   t1, 1
+    sw   t1, AXI_LLC_COMMIT_CFG_REG_OFFSET(t0)
     // Correct stack to start at end of SPM
-    la t0, __base_regs
-    la sp, __base_spm
-    lw t0, 84(t0)   // regs.LLC_SIZE
-    add sp, sp, t0
+    la   t0, __base_regs
+    la   sp, __base_spm
+    lw   t0, CHESHIRE_LLC_SIZE_REG_OFFSET(t0)
+    add  sp, sp, t0
     addi sp, sp, -8
 
 // Enter Platform ROM if present.
 _prom_check_run:
     // Note that we have internal access to SPM here *if and only if* there is an LLC.
     la t0, __base_regs
-    lw t0, 72(t0)   // regs.PLATFORM_ROM
+    lw t0, CHESHIRE_PLATFORM_ROM_REG_OFFSET(t0)
     beqz t0, _boot
     jalr t0
 
+// Move to next stage of booting
+// 1. Write the address of next stage boot loader in Cheshire's scratch registers
+// 2. Resume execution of all other harts 
 .global boot_next_stage
 boot_next_stage:
-    // Non-SMP hart: Write boot address into global scratch registers
-    la t0, __base_regs
-    sw a0, 16(t0)   // regs.SCRATCH[4]
+
+    // Non-SMP hart: write boot address into global scratch registers
+    la   t0, __base_regs
+    sw   a0, CHESHIRE_SCRATCH_4_REG_OFFSET(t0)
     srli a0, a0, 32
-    sw a0, 20(t0)   // regs.SCRATCH[5]
+    sw   a0, CHESHIRE_SCRATCH_5_REG_OFFSET(t0)
     fence
-    // Resume SMP harts
-    smp_resume(t0, t1, t2)
+
+    // Resume SMP harts: set CLINT IPI registers
+    // NOTE: this will cause CLINT to send IPIs to all cores, therefore also the 
+    // non-smp hart will receive one. The following instructions make sure that 
+    // all harts will wait until the IPI is received (WFI with global ie disabled),
+    // then clear the IPI in the CLINT and wait until all other harts are done with it. 
+    la   t0, __base_clint
+    la   t2, __base_regs
+    lw   t2, CHESHIRE_NUM_INT_HARTS_REG_OFFSET(t2)
+    slli t2, t2, 2
+    add  t2, t0, t2  // t2 = CLINT_BASE + (n_harts * 4)
+1:
+    li   t1, 1
+    sw   t1, 0(t0)
+    addi t0, t0, 4
+    blt  t0, t2, 1b
+
+// Stall hart until IPI is raised
+_wait_for_ipi:
+
+    // Wait until this hart receives IPI
+    wfi
+    csrr t1, mip
+    andi t1, t1, 0x8
+    beqz t1, _wait_for_ipi
+
+    // Clear CLINT IPI register for this hart
+    la   t0, __base_clint
+    csrr t1, mhartid
+    slli t1, t1, 2
+    add  t1, t1, t0
+    sw   zero, 0(t1)   // *(CLINT_BASE + hart_id * 4) = 0
+
+    la   t2, __base_regs
+    lw   t2, CHESHIRE_NUM_INT_HARTS_REG_OFFSET(t2)
+    slli t2, t2, 2
+    add  t2, t0, t2    // t2 = CLINT_BASE + (n_harts * 4)
+
+    // Wait until *all* CLINT IPI registers are cleared
+1:
+    lw   t1, 0(t0)
+    bnez t1, 1b
+    addi t0, t0, 4
+    blt  t0, t2, 1b
+
+    // Jump to next stage
     // Load boot address from global scratch registers
-    la t0, __base_regs
-    lwu t1, 20(t0)  // regs.SCRATCH[5]
+    la   t0, __base_regs
+    lwu  t1, CHESHIRE_SCRATCH_5_REG_OFFSET(t0)
     slli t1, t1, 32
-    lwu t0, 16(t0)  // regs.SCRATCH[4]
-    or t0, t0, t1
-    // Store hartid to a0
-    csrr a0, mhartid
-    // Jump to boot address
-    jalr ra, 0(t0)
-    // We should never get here
-    ret
+    lwu  t0, CHESHIRE_SCRATCH_4_REG_OFFSET(t0)
+    or   t0, t0, t1
+    csrr a0, mhartid  // Store hartid to a0
+    jalr ra, 0(t0)    // Jump to boot address
+    ret               // We should never get here
 
 // Reset regs, full fence, then jump to main
 _boot:
@@ -121,9 +175,10 @@ _boot:
 .global _exit
 _exit:
     // Save the return value to scratch register 2 and wait forever
+    // Set bit 0 to signal that the execution is done.
     slli a0, a0, 1
     ori  a0, a0, 1
     la t0, __base_regs
-    sw a0, 8(t0)     // regs.SCRATCH[2]
+    sw a0, CHESHIRE_SCRATCH_2_REG_OFFSET(t0)
 1:  wfi
     j 1b