idma wrapper
reviewdog [verible-verilog-lint] report
reported by reviewdog 🐶
Findings (9)
hw/cheshire_soc.sv|32 col 34| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1388 col 50| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1398 col 15| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1407 col 44| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1413 col 44| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/idma_core_wrap.sv|8 col 8| Declared module does not match the first dot-delimited component of file name: "idma_core_wrap" [Style: file-names] [module-filename]
hw/idma_core_wrap.sv|13 col 26| Non-type parameter names must be styled with CamelCase or ALL_CAPS [Style: constants] [parameter-name-style]
hw/idma_core_wrap.sv|14 col 26| Non-type parameter names must be styled with CamelCase or ALL_CAPS [Style: constants] [parameter-name-style]
hw/idma_core_wrap.sv|229 col 10| File must end with a newline. [Style: posix-file-endings] [posix-eof]
Filtered Findings (0)
Annotations
Check warning on line 32 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L32
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:32 column:34}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:32 column:34} end:{line:33}} text:" input logic eth_clk_90,\n"}
Check warning on line 1388 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L1388
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:1388 column:50}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1388 column:50} end:{line:1389}} text:" .DataWidth ( Cfg.AxiDataWidth ),\n"}
Check warning on line 1398 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L1398
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:1398 column:15}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1398 column:15} end:{line:1399}} text:" .rst_ni,\n"}
Check warning on line 1407 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L1407
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:1407 column:44}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1407 column:44} end:{line:1408}} text:" .phy_resetn_o ( eth_rstn_o ),\n"}
Check warning on line 1413 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L1413
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:1413 column:44}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1413 column:44} end:{line:1414}} text:" .phy_mdc_o ( eth_mdc_o ),\n"}
Check warning on line 8 in hw/idma_core_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/idma_core_wrap.sv#L8
Declared module does not match the first dot-delimited component of file name: "idma_core_wrap" [Style: file-names] [module-filename]
Raw output
message:"Declared module does not match the first dot-delimited component of file name: \"idma_core_wrap\" [Style: file-names] [module-filename]" location:{path:"hw/idma_core_wrap.sv" range:{start:{line:8 column:8}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 13 in hw/idma_core_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/idma_core_wrap.sv#L13
Non-type parameter names must be styled with CamelCase or ALL_CAPS [Style: constants] [parameter-name-style]
Raw output
message:"Non-type parameter names must be styled with CamelCase or ALL_CAPS [Style: constants] [parameter-name-style]" location:{path:"hw/idma_core_wrap.sv" range:{start:{line:13 column:26}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 14 in hw/idma_core_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/idma_core_wrap.sv#L14
Non-type parameter names must be styled with CamelCase or ALL_CAPS [Style: constants] [parameter-name-style]
Raw output
message:"Non-type parameter names must be styled with CamelCase or ALL_CAPS [Style: constants] [parameter-name-style]" location:{path:"hw/idma_core_wrap.sv" range:{start:{line:14 column:26}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 229 in hw/idma_core_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/idma_core_wrap.sv#L229
File must end with a newline. [Style: posix-file-endings] [posix-eof]
Raw output
message:"File must end with a newline. [Style: posix-file-endings] [posix-eof]" location:{path:"hw/idma_core_wrap.sv" range:{start:{line:229 column:10}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:229 column:10} end:{line:230}} text:"endmodule\n"}