Merge pull request #10 from py32-rust/py32f040

Py32f040

Author: gpgreen

CHANGELOG.md

@@ -2,7 +2,24 @@
 
 All notable changes to this project will be documented in this file.
 
-## v0.2.0
+## v0.2.1 2025-01-28
+
+### Added
+
+ - Added array access to timer CCR registers
+ - Added py32f040 device
+ - `scripts/README.md` to show usage of scripts
+ - modified scripts to handle `bitRange` vs `bitOffset` and `bitWidth` usage in svd files
+
+### Changed
+
+ - Renamed field `DBG_TIM14_STOP` to `DBG_TIMER14_STOP` in `DBG` peripheral for py32f002b to make it consistent with other devices
+
+### Removed
+
+ - Removed renaming of timer CCR registers
+
+## v0.2.0 2024-12-28
 
 ### Added
 
@@ -17,11 +34,11 @@ All notable changes to this project will be documented in this file.
  - Updated form version from 0.10.0 to 0.12.1
  - Updated svdtools version from 0.3.0 to 0.3.14
 
-## v0.1.1
+## v0.1.1 2024-10-10
 
-## V0.1.0
+## V0.1.0 2024-09-27
 
-## v0.0.1
+## v0.0.1 2023-06-10
 
  - Original Release
 

README.md

@@ -26,7 +26,7 @@ make any guarantee of correctness. Please report any bugs you find!
 In your own project's `Cargo.toml`:
 ```toml
 [dependencies.py32f0]
-version = "0.1.1"
+version = "0.2.1"
 features = ["py32f030"]
 ```
 

devices/common_patches/adc_rw.yaml

@@ -0,0 +1,4 @@
+SR:
+  _modify:
+    OVER:
+      access: read-write

devices/common_patches/f002b_dbg.yaml

@@ -0,0 +1,4 @@
+APB_FZ2:
+  _modify:
+    DBG_TIM14_STOP:
+      name: DBG_TIMER14_STOP

devices/common_patches/flash_f040_rename.yaml

@@ -0,0 +1,4 @@
+OPTR:
+  _modify:
+    NBOOT1:
+      name: nBOOT1

devices/common_patches/rtc_040_renames.yaml

@@ -0,0 +1,35 @@
+PRLH:
+  _modify:
+    PRL:
+      name: PRLH
+PRLL:
+  _modify:
+    PRL:
+      name: PRLL
+DIVH:
+  _modify:
+    DIV:
+      name: DIVH
+DIVL:
+  _modify:
+    DIV:
+      name: DIVL
+CNTH:
+  _modify:
+    RTC_CNT:
+      name: CNTH
+CNTL:
+  _modify:
+    RTC_CNT:
+      name: CNTL
+ALRH:
+  _modify:
+    RTC_ALR:
+      name: ALRH
+ALRL:
+  _modify:
+    RTC_ALR:
+      name: ALRL
+_modify:
+  BKP_RTCCR:
+    name: RTCCR

devices/common_patches/timer_ccr_reg_array.yaml

@@ -0,0 +1,2 @@
+_array:
+    CCR*: {}

devices/common_patches/usart_f040_rename.yaml

@@ -0,0 +1,10 @@
+BRR:
+  _modify:
+    DIV_FRACTION:
+      name: DIV_Fraction
+    DIV_MANTISSA:
+      name: DIV_Mantissa
+CR3:
+  _modify:
+    ABRMODE:
+      name: ABRMOD

devices/py32f002a.yaml

@@ -8,6 +8,10 @@ _svd: ../svd/py32f002a.svd
   _include:
     - common_patches/usart_dr8.yaml
 
+TIM1:
+  _include:
+    - common_patches/timer_ccr_reg_array.yaml
+
 _include:
  - ./common_patches/pwr_f002a.yaml
  - ./common_patches/syscfg_f002a.yaml

devices/py32f002b.yaml

@@ -9,6 +9,14 @@ _svd: ../svd/py32f002b.svd
   _include:
     - common_patches/usart_dr8.yaml
 
+"DBG":
+  _include:
+    - common_patches/f002b_dbg.yaml
+
+"TIM*":
+  _include:
+    - common_patches/timer_ccr_reg_array.yaml
+
 _include:
  - ./common_patches/syscfg_f002b.yaml
  - ../peripherals/flash/flash_f002b.yaml