Difference compared to uvm-python package

[msrasheed]

Forgive me if this is posted somewhere already, but how does this project aim to be different from the uvm-python package? From what I can tell it is a more complete port but also hasn't been active for a year.

[raysalemi]

Forgive me if this is posted somewhere already, but how does this project aim to be different from the uvm-python package? From what I can tell it is a more complete port but also hasn't been active for a year.

That project is the result of running a script on the SystemVerilog code. This project is a completely clean write from the spec. I also cleaned up parts of the spec that weren't needed for Python such as the _imp classes.

I also refactored some things such as the ConfigDB and support the logging module rather than implement the reporting system in UVM.