super heterodyne

[jordens]

With Pounder, or any other phase-like signal (PDH, fiber length, phase lock) for that matter, it would be adequate and beneficial to not convert to DC before the ADCs but to a high IF (higher than the loop bandwidth) and then perform the rest of the processing in the CPU. As the title says, this is nothing but a version of the > 100 year old super heterodyne combined with some modern SDR.

This gives:

• free phase gain calibration
• free amplitude monitoring and potentially power stabilization
• free rejection of LO harmonic aliases (even when not caught by the analog LP or when introduced after it)
• option for easy and proper AM crosstalk suppression
• no 1/f noise and low-f interference
• quadrature sensing
• operation at some power independent phase offset
• proper and infinite phase wrap tracking
• thus arbitrary capture range into the right fringe (nice for "integrator hold" use cases)

Needs:

• check dynamic range (required for quadrature sampling) vs noise (AFE gain can be high when operating at zero and DC): looks fine for all relevant locks at PTB at least
• check aliasing constraints (w.r.t sampling rate and analog bandwidth)
• check useful IF: in the range of loop bandwidth up to the analog bandwidth minus loop bandwidth, don't get the SMPS spurs into the bandwidth
• check DDS ref clock/LO vs ADC sample clock synchronization and requirements for ADC sample phase tracking (to e.g. DDS SYNC), use sync with timer capture to tag adc samples, fix SYNC_CLK to Stabilizer ETR/CHx timer input sinara-hw/Pounder#76

Context:

• Pounder support (Pounder support #41)
• ties into the lock-in mode (lock-in #60)
• Pounder synchronization (SYNC_CLK to Stabilizer ETR/CHx timer input sinara-hw/Pounder#76)

[jordens]

All done.