Fix Flattening In Symbol Table

[David-Durst]

As seen in phanrahan/magma#287, there are issues in viewing the values of nested ports in the Magma simulator that is based on the CoreIR simulator. The simulator crashes as it can't find the correct values in the symbol table. For example, https://github.com/David-Durst/aetherling/blob/ed4a632ef935dc79fe991677300a8e092ed9df4b/tests/test_native_2d_line_buffer.py#L371 requires using the wrong parent scope (scope instead of the properly nested test1_scope). If that line is written as:

test2_scope = Scope(instance=LineBufferDef._instances[0]._instances[0], parent=test1_scope)

the simulator fails immediately. (NOTE: if you want to reproduce this, you must checkout the exact Aetherling commit that I linked to. I have since removed these nested accesses as they don't work)

Fixing this symbol table issue would significantly improve the development process in magma. Currently, because I can't access nested wires, I need to send these wires to the top level of a circuit in order to view them while debugging. This is quite difficult to do when creating deeply nested, dynamically generated circuits. Using the debugger with the symbol table is much faster.