Draft of Zfh extension for IEEE 754 binary16 support #496
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Any plan for merge this? I think it's just 0.1 that mean we still have chance to change anything? otherwise it's like a hidden/secret extension in branch. When I said there is already have a spec draft for zfh/fp16 and then people told me they don't seem the spec, that happened several times, and then I need to point out this is not exist in master branch yet, you need to find it out in |
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I would love to merge it, but IIRC the plan was to wait until @kasanovic wrote an email proposing it. |
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Oh, OK, thanks for clarification :) |
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I really hope this PR could merge and freeze soon, this is a very useful extension. |
src/zfh.tex
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| half-precision operands to single-precision, performing the operation | ||
| using single-precision arithmetic, then converting back to half-precision. | ||
| Performing half-precision fused multiply-addition using this method incurs | ||
| a 1-ulp error on some inputs. |
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Suggest clarifying that the "error" is only on RNE and RMM (double-rounding is innocuous for directed rounding).
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@knightsifive Yeah, good point.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Co-authored-by: Chih-Min Chao <cmchao@gmail.com>
Signed-off-by: Chih-Min Chao <cmchao@gmail.com> Co-authored-by: Chih-Min Chao <cmchao@gmail.com>
This proposal follows the template of the existing FP extensions. Future extensions might also provide widening ops, but I think that's out of scope for the baseline.