rkdgmlqja / FPGA_DoorLock Public

Notifications You must be signed in to change notification settings
Fork 0
Star 2

simple project using zybo z7 20 which goal is to design fully functioning doorlock

2 stars 0 forks Branches Tags Activity

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
codes		codes
README.md		README.md

Repository files navigation

FPGA_DoorLock

Abstract

simple project using zybo z7 20 which goal is to design fully functioning doorlock

HW

Zyboz7 20

Block Diagram

State diagram

Verification(Demo)

doorlock.mp4

About

simple project using zybo z7 20 which goal is to design fully functioning doorlock

fpga verilog fpga-programming

Report repository

Releases

No releases published

Packages

No packages published

Languages

Verilog 100.0%