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Release v6.56.0
What's Changed
- feat(pdk,pnr): per-PDK placement, PDN, dont-use cells and CTS buffer list (#101) by @hernloh in #625
- feat(synth): gate unbound SystemVerilog interface instances by @hernloh in #629
- fix(power): feed macro Liberty to rb power and flag zero-power macros (#627) by @hernloh in #630
- fix(pnr): size-aware macro packing with a PDN-safe halo (#626) by @hernloh in #632
- feat(pnr): apply per-run pin constraints after floorplan initialization by @expsg-hern in #633
Full Changelog: v6.55.0...v6.56.0