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Sign upTracking issue for float_bits_conv feature #40470
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alexcrichton
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Hmm, seems this feature has broken the ieee754 crate:
Apparently you can't shadow functions with a trait: https://is.gd/oKiVZH (the first assert works, but the second fails) |
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Is the issue above something we have to fix, or rather something the |
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@est31 RFC 1105 laid out that adding inherent methods is a minor change so it's up to the team(s) to decide whether we're okay with the practical impact of the change. |
brson
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May 6, 2017
Closed
Rust 1.18 regression - ieee754-0.2.1, from_bits #41793
sunfishcode
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Jun 6, 2017
Closed
Remove use of unsafe transmute in read_f32 and read_f64 #14
This was referenced Jun 26, 2017
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cc #43025 --- with this merged, could we get this feature stabilized in Rust 1.20? |
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rfcbot
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Jul 4, 2017
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Team member @BurntSushi has proposed to merge this. The next step is review by the rest of the tagged teams: No concerns currently listed. Once these reviewers reach consensus, this will enter its final comment period. If you spot a major issue that hasn't been raised at any point in this process, please speak up! See this document for info about what commands tagged team members can give me. |
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@rfcbot reviewed |
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rfcbot
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rfcbot
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rfcbot
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Jul 16, 2017
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The final comment period is now complete. |
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rfcbot
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Jul 16, 2017
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The final comment period is now complete. |
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Really late to this party. As I note here, the NaN masking is unnecessary from LLVM's perspective. I'm not totally clear on the platform-specific-NaN-reprs issue, but at least on x86/x64, we can just make If we wish to do so, this just leaves the following question: do we ignore the existence of non-2008-compliant hardware (transmute on all platforms) or do we allow behaviour to be platform-specific (transmute only on definitely-2008-compliant hardware)? |
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I'm certainly on board with just transmuting on architectures we know are okay. |
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Transmuting should be safe on ARM & AArch64. The only issue is whether a sNaN can cause a trap when it is used. By default floating-point exception are masked on ARM/AArch64, but can be enabled by setting some bits in the These bits also allow enabling exceptions for situations like inexact floating-point rounding, float division by zero, etc. These operations are all supported in safe Rust, so I suggest that the official Rust policy be something along the lines: "Rust assumes that all floating-point operations do not trap." |
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I don't think we really care if the operation traps, right? It's not unsafe to do so. |
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We do care if the trap is considered an "observable side-effect" of the operation, since this affects optimization. This would impact dead code elimination for example: you would still have to trigger the trap even if the result of the operation is not used. |
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Ah sure that makes sense. |
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very interesting! We need more people like you :). I am personally okay with anything (the documentation was made vague purposefully!), but before we commit to anything that we can't reverse (e.g. making docs super clear that it is only a transmute), I'd love to get @Gankro 's LLVM patch merged upstream so that it has been reviewed by LLVM reviewers and deemed okay. |
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Unfortunately, it is still necessary from LLVM's perspective; see https://github.com/llvm-mirror/llvm/blob/master/lib/Analysis/InstructionSimplify.cpp#L4142 for example. I support changing LLVM's behavior here, but this isn't just a case of fixing mistaken documentation; it's changing the policy, so we need to be careful. |
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Interesting. That transformation is justified by sNaN being bad, but in fact doesn't look for sNaN. Rather it looks for undef, and up to this point we've fairly conservatively considered doing ~anything with undef to be UB for Rust (because undef is poorly defined and we don't want to couple with LLVM semantics anyway). As such, the existence of that transformation shouldn't actually be a barrier to us making this change? (we should still fix llvm as well) |
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FWIW, that change originally came from here: llvm-mirror/llvm@50b2ca4 |
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@Gankro That's a good point. Allowing Rust to produce sNaNs in more places doesn't break those kinds of optimizations. And I'm not aware of any optimizations that explicitly check for sNaNs, and I've checked all the usual suspects. So this change seems ok. |
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cc #46246 |
est31 commentedMar 13, 2017
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edited
Tracking issue for the conversion
float_bits_convfeature, added by PR #39271.The main topic during the PR's thread has been about how to handle signaling NaNs, and the final decision was to silently mask them, especially as LLVM behaviour regarding them is not well specified.
Another issue raised by @dwrensha was that sNaNs are not encoded consistently. IEEE 754-2008 (section 8.2.1 in the latest draft) specifies quiet NaNs to have their first bit of the trailing significand field set to 1, for signaling NaNs it should be set to 0. Some MIPS based platforms have it reversed. Should they be cfg'd out?