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Fix target-cpu fpu features on Arm R/M-profile #123159

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merged 1 commit into from
Apr 6, 2024
Merged

Fix target-cpu fpu features on Arm R/M-profile #123159

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2 changes: 1 addition & 1 deletion compiler/rustc_target/src/spec/targets/armebv7r_none_eabihf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ pub fn target() -> Target {
linker: Some("rust-lld".into()),
relocation_model: RelocModel::Static,
panic_strategy: PanicStrategy::Abort,
features: "+vfp3,-d32,-fp16".into(),
features: "+vfp3d16".into(),
max_atomic_width: Some(64),
emit_debug_gdb_scripts: false,
// GCC defaults to 8 for arm-none here.
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2 changes: 1 addition & 1 deletion compiler/rustc_target/src/spec/targets/armv7r_none_eabihf.rs
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Expand Up @@ -21,7 +21,7 @@ pub fn target() -> Target {
linker: Some("rust-lld".into()),
relocation_model: RelocModel::Static,
panic_strategy: PanicStrategy::Abort,
features: "+vfp3,-d32,-fp16".into(),
features: "+vfp3d16".into(),
max_atomic_width: Some(64),
emit_debug_gdb_scripts: false,
// GCC defaults to 8 for arm-none here.
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13 changes: 6 additions & 7 deletions compiler/rustc_target/src/spec/targets/thumbv7em_none_eabihf.rs
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Expand Up @@ -25,16 +25,15 @@ pub fn target() -> Target {

options: TargetOptions {
abi: "eabihf".into(),
// `+vfp4` is the lowest common denominator between the Cortex-M4 (vfp4-16) and the
// Cortex-M7 (vfp5)
// `-d32` both the Cortex-M4 and the Cortex-M7 only have 16 double-precision registers
// available
// `-fp64` The Cortex-M4 only supports single precision floating point operations
// whereas in the Cortex-M7 double precision is optional
// vfp4 is the lowest common denominator between the Cortex-M4F (vfp4) and the
// Cortex-M7 (vfp5).
// Both the Cortex-M4 and the Cortex-M7 only have 16 double-precision registers
// available, and the Cortex-M4 only supports single-precision floating point operations
// whereas in the Cortex-M7 double-precision is optional.
//
// Reference:
// ARMv7-M Architecture Reference Manual - A2.5 The optional floating-point extension
features: "+vfp4,-d32,-fp64".into(),
features: "+vfp4d16sp".into(),
max_atomic_width: Some(32),
..base::thumb::opts()
},
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3 changes: 1 addition & 2 deletions compiler/rustc_target/src/spec/targets/thumbv8m_main_none_eabihf.rs
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Expand Up @@ -22,8 +22,7 @@ pub fn target() -> Target {
// processor, the Cortex-M33 Technical Reference Manual states that
// the FPU uses the FPv5 architecture, single-precision instructions
// and 16 D registers.
// These parameters map to the following LLVM features.
features: "+fp-armv8,-fp64,-d32".into(),
features: "+fp-armv8d16sp".into(),
max_atomic_width: Some(32),
..base::thumb::opts()
},
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