Skip to content

Conversation

pmur
Copy link
Contributor

@pmur pmur commented Sep 23, 2025

This should address the last(?) missing pieces of inline asm for ppc:

  • Explicit VSX register support. ISA 2.06 (POWER7) added a 64x128b register overlay extending the fpr's to 128b, and unifies them with the vmx (altivec) registers. Implementations details within gcc/llvm percolate up, and require using the x template modifier. I have updated the inline asm to implicitly include this for vsx arguments which do not specify it. Support for the gcc codegen backend is still a todo.

  • Implement the preserves_flags option. All ABI's, and all ISAs store their flags in cr, and the carry bit lives inside xer. The other status registers hold sticky bits or control bits which do not affect branch instructions.

There is some interest in the e500 (powerpcspe) port. Architecturally, it has a very different FP ISA, and includes a simd extension called SPR (which is not IBM's cell SPE). Notably, it does not have altivec/fpr/vsx registers. It also has an SPE accumulator register which its ABI marks as volatile, but I am not sure if the compiler uses it.

Where supported, VSX is a 64x128b register set which encompasses
both the floating point and vector registers.

In the type tests, xvsqrtdp is used as it is the only two-argument
vsx opcode supported by all targets on llvm. If you need to copy
a vsx register, the preferred way is "xxlor xt, xa, xa".
Treat cr (cr0-cr7) and xer as preserved flags if the inline_asm option
is specified. fpscr and vscr are not tracked as they contain sticky bits
which are generally assumed to be volatile, but do not contains flags
used to control branches.
@rustbot rustbot added A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. labels Sep 23, 2025
@rustbot
Copy link
Collaborator

rustbot commented Sep 23, 2025

r? @jackh726

rustbot has assigned @jackh726.
They will have a look at your PR within the next two weeks and either review your PR or reassign to another reviewer.

Use r? to explicitly pick a reviewer

@pmur
Copy link
Contributor Author

pmur commented Sep 23, 2025

r? @Amanieu
cc @taiki-e

@rustbot rustbot assigned Amanieu and unassigned jackh726 Sep 23, 2025
@rust-log-analyzer
Copy link
Collaborator

The job pr-check-2 failed! Check out the build log: (web) (plain enhanced) (plain)

Click to see the possible cause of the failure (guessed by this bot)
    Checking tempfile v3.20.0
[RUSTC-TIMING] tempfile test:false 0.113
[RUSTC-TIMING] object test:false 1.952
    Checking rustc_codegen_gcc v0.1.0 (/checkout/compiler/rustc_codegen_gcc)
error[E0004]: non-exhaustive patterns: `rustc_target::asm::InlineAsmRegClass::PowerPC(rustc_target::asm::PowerPCInlineAsmRegClass::vsreg)` not covered
   --> compiler/rustc_codegen_gcc/src/asm.rs:654:11
    |
654 |     match reg_class {
    |           ^^^^^^^^^ pattern `rustc_target::asm::InlineAsmRegClass::PowerPC(rustc_target::asm::PowerPCInlineAsmRegClass::vsreg)` not covered
    |
note: `rustc_target::asm::InlineAsmRegClass` defined here
   --> /checkout/compiler/rustc_target/src/asm/mod.rs:474:1
    |
474 | pub enum InlineAsmRegClass {
---
    = note: the matched value is of type `rustc_target::asm::InlineAsmRegClass`
help: ensure that all possible cases are being handled by adding a match arm with a wildcard pattern or an explicit pattern as shown
    |
740 ~         InlineAsmRegClass::Err => unreachable!(),
741 ~         rustc_target::asm::InlineAsmRegClass::PowerPC(rustc_target::asm::PowerPCInlineAsmRegClass::vsreg) => todo!(),
    |

error[E0004]: non-exhaustive patterns: `rustc_target::asm::InlineAsmRegClass::PowerPC(rustc_target::asm::PowerPCInlineAsmRegClass::vsreg)` not covered
   --> compiler/rustc_codegen_gcc/src/asm.rs:747:11
    |
747 |     match reg {
    |           ^^^ pattern `rustc_target::asm::InlineAsmRegClass::PowerPC(rustc_target::asm::PowerPCInlineAsmRegClass::vsreg)` not covered
    |
note: `rustc_target::asm::InlineAsmRegClass` defined here
   --> /checkout/compiler/rustc_target/src/asm/mod.rs:474:1
    |
474 | pub enum InlineAsmRegClass {
---
    = note: the matched value is of type `rustc_target::asm::InlineAsmRegClass`
help: ensure that all possible cases are being handled by adding a match arm with a wildcard pattern or an explicit pattern as shown
    |
837 ~         InlineAsmRegClass::Err => unreachable!(),
838 ~         rustc_target::asm::InlineAsmRegClass::PowerPC(rustc_target::asm::PowerPCInlineAsmRegClass::vsreg) => todo!(),
    |

For more information about this error, try `rustc --explain E0004`.
[RUSTC-TIMING] rustc_codegen_gcc test:false 1.206
error: could not compile `rustc_codegen_gcc` (lib) due to 2 previous errors

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
Projects
None yet
Development

Successfully merging this pull request may close these issues.

5 participants