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rustc_target: RISC-V: Add two supervisor extensions for intrinsics #147439

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rustc_target: RISC-V: Add two supervisor extensions for intrinsics #147439

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5 changes: 5 additions & 0 deletions compiler/rustc_target/src/target_features.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -599,6 +599,7 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[
Stability::Forbidden { reason: "unsound because it changes the ABI of atomic operations" },
&[],
),
("h", Unstable(sym::riscv_target_feature), &["zicsr"]),
("m", Stable, &[]),
("relax", Unstable(sym::riscv_target_feature), &[]),
(
Expand Down Expand Up @@ -644,6 +645,7 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[
],
),
("supm", Unstable(sym::riscv_target_feature), &[]),
("svinval", Unstable(sym::riscv_target_feature), &[]),
("unaligned-scalar-mem", Unstable(sym::riscv_target_feature), &[]),
("unaligned-vector-mem", Unstable(sym::riscv_target_feature), &[]),
("v", Unstable(sym::riscv_target_feature), &["zvl128b", "zve64d"]),
Expand Down Expand Up @@ -1147,6 +1149,9 @@ impl Target {
// Note that the `e` feature is not required: the ABI treats the extra
// registers as caller-save, so it is safe to use them only in some parts of
// a program while the rest doesn't know they even exist.
// For the same reason, this ABI is *not* stated incompatible with `h`,
// which requires a base integer ISA with 32 general purpose registers
// and is incompatible with the `e` feature.
FeatureConstraints { required: &[], incompatible: &["d"] }
}
"lp64e" => {
Expand Down
2 changes: 2 additions & 0 deletions tests/ui/check-cfg/target_feature.stderr
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Expand Up @@ -124,6 +124,7 @@ LL | cfg!(target_feature = "_UNEXPECTED_VALUE");
`fxsr`
`gfni`
`guarded-storage`
`h`
`hard-float`
`hard-float-abi`
`hard-tp`
Expand Down Expand Up @@ -314,6 +315,7 @@ LL | cfg!(target_feature = "_UNEXPECTED_VALUE");
`sve2-sha3`
`sve2-sm4`
`sve2p1`
`svinval`
`tail-call`
`tbm`
`thumb-mode`
Expand Down
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