Add support for Hexagon v60 HVX intrinsics #41818
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The changes look fairly straightforward to me. I have a question though. Is |
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Yeah, it's in the documentation and headers. Unfortunately the documentation and headers are buried in their SDK. You can get it from https://developer.qualcomm.com/software/hexagon-dsp-sdk/tools . v3.1 doesn't require registration to download. There's an installer, but you can just unzip it, and then unzip a jar ( Pretty terrible. I think there's one example of an open source project using HVX (halide), but they seem to use llvm ir directly rather than C intrinsics. It's actually more generic than HVX though - I see the Q6 prefix on other intrinsics too. I'm guessing it's something like Q = Qualcomm, 6 = Hexagon. |
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@bors r+ |
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📌 Commit cc4efd1 has been approved by |
Add support for Hexagon v60 HVX intrinsics HVX is a SIMD coprocessor available on newer hexagon cores. It can be configured for 512 or 1024 bit registers, and some instructions use pairs of registers. It only does integer operations, but it probably has every integer operation you'd want for 8/16/32 bit elements. There are a lot of intrinsics. The generator outputs 582 of them. I probably got some wrong. I did some scripting to make sure that every llvm intrinsic name exists, but intrinsic names provided for programs have only been compared by eye to Qualcomm's own names. 64/128 is also appended to the names to select between 512/1024 bit. The C intrinsics don't do this, but they only expose one set, selected at compile time. The json specifying the intrinsics required a bit of duplication since I didn't see an easy way to specify combinations of signed/unsigned types (eg. u(8-16) and s(16-32)). I also didn't see an easy way to specify variants of instructions like saturating or rounding. Basic multiplication and load/store tested on the hexagon simulator.
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☀️ Test successful - status-appveyor, status-travis |
HVX is a SIMD coprocessor available on newer hexagon cores. It can be configured for 512 or 1024 bit registers, and some instructions use pairs of registers. It only does integer operations, but it probably has every integer operation you'd want for 8/16/32 bit elements.
There are a lot of intrinsics. The generator outputs 582 of them. I probably got some wrong. I did some scripting to make sure that every llvm intrinsic name exists, but intrinsic names provided for programs have only been compared by eye to Qualcomm's own names. 64/128 is also appended to the names to select between 512/1024 bit. The C intrinsics don't do this, but they only expose one set, selected at compile time.
The json specifying the intrinsics required a bit of duplication since I didn't see an easy way to specify combinations of signed/unsigned types (eg. u(8-16) and s(16-32)). I also didn't see an easy way to specify variants of instructions like saturating or rounding.
Basic multiplication and load/store tested on the hexagon simulator.