RISC-V: Use symbolic instructions on inline assembly (part 2) #1936
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
While many intrinsics use
.insn
to generate raw machine code from numbers, all ratified instructions can be now symbolic.This is the part two (after the
pause
intrinsic) and uses a different way to use symbolic instructions.Normally, intrinsics require corresponding extensions and this commit uses newly added Rust target features
h
andsvinval
(both representing supervisor-mode extensions), along with the#[target_feature(enable = ...)]
attribute.Note
hinval.vvma
andhinval.gvma
instructions are a part of the Svinval extension (the H extension is not directly required by LLVM) but denoted to require bothh
andsvinval
to show semantic context (they are useful only when the H extension is present and according to the documentation, they are provided only if the hypervisor extension is enabled).This is the part two after #1927 (currently, this is the superset of it) and requires some Rust compiler changes (adding target features
h
andsvinval
; so CI should fail as of this writing).