sha1dc 0.1.4 brings an SSE2 compression to x86 CPUs without SHA-NI, which
hashes 19–26% faster than 0.1.3 on Intel chips before Ice Lake such as
Cascade Lake. With SHA-NI, it is 6–7% faster on a Sapphire Rapids Xeon,
2–4% on Ice Lake and about 1% on large inputs on Zen.

Notable changes:

- x86 without SHA-NI has an SSE2 compression that builds the schedule four
  words at a time, where the portable one expands it a word at a time
  (#33). The x86 backends live under backend/x86, and SHA-NI's detection
  sits behind a token, so the dispatch needs no `unsafe`.
- SHA-NI builds words 32 to 79 of the schedule by a recurrence that needs
  no sha1msg2, which Sapphire Rapids microcodes, and is built with AVX
  where there is AVX (#32). The AVX2 filter's prefix grows to 16 groups.
- aarch64-unknown-none-softfloat takes the scalar forms rather than
  enabling NEON per function, which rustc flags as future-incompatible
  (#30). CI tests every Tier 1 target, and wasm32-wasip1 under wasmtime.