DRM driver cleanups

Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml

@@ -51,7 +51,7 @@ properties:
 
   dma-channels:
     minimum: 1
-    maximum: 8
+    maximum: 16
 
   resets:
     maxItems: 1
@@ -74,14 +74,14 @@ properties:
       Channel priority specifier associated with the DMA channels.
     $ref: /schemas/types.yaml#/definitions/uint32-array
     minItems: 1
-    maxItems: 8
+    maxItems: 16
 
   snps,block-size:
     description: |
       Channel block size specifier associated with the DMA channels.
     $ref: /schemas/types.yaml#/definitions/uint32-array
     minItems: 1
-    maxItems: 8
+    maxItems: 16
 
   snps,axi-max-burst-len:
     description: |

Documentation/devicetree/bindings/hwmon/starfive,jh7100-temp.yaml

@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/starfive,jh7100-temp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7100 Temperature Sensor
+
+maintainers:
+  - Emil Renner Berthing <kernel@esmil.dk>
+
+description: |
+  StarFive Technology Co. JH7100 embedded temperature sensor
+
+properties:
+  compatible:
+    enum:
+      - starfive,jh7100-temp
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 2
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: "sense"
+      - const: "bus"
+
+  '#thermal-sensor-cells':
+    const: 0
+
+  interrupts:
+    maxItems: 1
+
+  resets:
+    minItems: 2
+    maxItems: 2
+
+  reset-names:
+    items:
+      - const: "sense"
+      - const: "bus"
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive-jh7100.h>
+    #include <dt-bindings/reset/starfive-jh7100.h>
+
+    tmon: tmon@124a0000 {
+        compatible = "starfive,jh7100-temp";
+        reg = <0x124a0000 0x10000>;
+        clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
+                 <&clkgen JH7100_CLK_TEMP_APB>;
+        clock-names = "sense", "bus";
+        #thermal-sensor-cells = <0>;
+        interrupts = <122>;
+        resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
+                 <&rstgen JH7100_RSTN_TEMP_APB>;
+        reset-names = "sense", "bus";
+    };

Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml

@@ -88,6 +88,10 @@ properties:
     $ref: /schemas/types.yaml#/definitions/uint32
     enum: [0, 1, 2, 3, 4, 5, 6]
 
+  starfive,keep-gpiomux:
+    description: Keep pinmux for these GPIOs from being reset at boot.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/reset/starfive,jh7100-audrst.yaml

@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/starfive,jh7100-audrst.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7100 SoC Audio Reset Controller Device Tree Bindings
+
+maintainers:
+  - Emil Renner Berthing <kernel@esmil.dk>
+
+properties:
+  compatible:
+    enum:
+      - starfive,jh7100-audrst
+
+  reg:
+    maxItems: 1
+
+  "#reset-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    reset-controller@10490000 {
+        compatible = "starfive,jh7100-audrst";
+        reg = <0x10490000 0x10000>;
+        #reset-cells = <1>;
+    };
+
+...

Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml

@@ -27,6 +27,7 @@ select:
         enum:
           - sifive,fu540-c000-ccache
           - sifive,fu740-c000-ccache
+          - starfive,jh7100-ccache
 
   required:
     - compatible
@@ -37,6 +38,7 @@ properties:
       - enum:
           - sifive,fu540-c000-ccache
           - sifive,fu740-c000-ccache
+          - starfive,jh7100-ccache
       - const: cache
 
   cache-block-size:

Documentation/hwmon/index.rst

@@ -177,6 +177,7 @@ Hardware Monitoring Kernel Drivers
    sch5627
    sch5636
    scpi-hwmon
+   sfctemp
    sht15
    sht21
    sht3x

Documentation/hwmon/sfctemp.rst

@@ -0,0 +1,32 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Kernel driver sfctemp
+=====================
+
+Supported chips:
+ - StarFive JH7100
+
+Authors:
+ - Emil Renner Berthing <kernel@esmil.dk>
+
+Description
+-----------
+
+This driver adds support for reading the built-in temperature sensor on the
+JH7100 RISC-V SoC by StarFive Technology Co. Ltd.
+
+``sysfs`` interface
+-------------------
+
+The temperature sensor can be enabled, disabled and queried via the standard
+hwmon interface in sysfs under ``/sys/class/hwmon/hwmonX`` for some value of
+``X``:
+
+================ ==== =============================================
+Name             Perm Description
+================ ==== =============================================
+temp1_enable     RW   Enable or disable temperature sensor.
+                      Automatically enabled by the driver,
+                      but may be disabled to save power.
+temp1_input      RO   Temperature reading in milli-degrees Celsius.
+================ ==== =============================================

MAINTAINERS

@@ -18153,6 +18153,14 @@ L:	netdev@vger.kernel.org
 S:	Supported
 F:	drivers/net/ethernet/sfc/
 
+SFCTEMP HWMON DRIVER
+M:	Emil Renner Berthing <kernel@esmil.dk>
+L:	linux-hwmon@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/hwmon/starfive,jh7100-temp.yaml
+F:	Documentation/hwmon/sfctemp.rst
+F:	drivers/hwmon/sfctemp.c
+
 SFF/SFP/SFP+ MODULE SUPPORT
 M:	Russell King <linux@armlinux.org.uk>
 L:	netdev@vger.kernel.org
@@ -19119,12 +19127,12 @@ F:	Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
 F:	drivers/pinctrl/pinctrl-starfive.c
 F:	include/dt-bindings/pinctrl/pinctrl-starfive.h
 
-STARFIVE JH7100 RESET CONTROLLER DRIVER
+STARFIVE JH7100 RESET CONTROLLER DRIVERS
 M:	Emil Renner Berthing <kernel@esmil.dk>
 S:	Maintained
-F:	Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
-F:	drivers/reset/reset-starfive-jh7100.c
-F:	include/dt-bindings/reset/starfive-jh7100.h
+F:	Documentation/devicetree/bindings/reset/starfive,jh7100-*.yaml
+F:	drivers/reset/starfive/reset-starfive-jh7100*
+F:	include/dt-bindings/reset/starfive-jh7100*.h
 
 STATIC BRANCH/CALL
 M:	Peter Zijlstra <peterz@infradead.org>

README.md

@@ -0,0 +1,154 @@
+# Linux kernel for StarFive's JH7100 RISC-V SoC
+
+## What is this?
+
+The [JH7100][soc] is a Linux-capable dual-core 64bit RISC-V SoC and this tree
+is meant to collect all the in-development patches for running Linux on boards
+using this. So far there are two such boards and both are supported by this tree:
+
+1) [StarFive VisionFive][visionfive]
+2) [BeagleV Starlight Beta][starlight]
+
+The VisionFive boards aren't quite shipping yet, but you can already
+[register interest][interest] and ask questions on the [forum][].
+
+About 300 BeagleV Starlight Beta boards were sent out to developers in
+April 2021 in preparation for an eventual BeagleV branded board using the
+updated JH7110 chip. The BeagleBoard organization has since [cancelled that
+project][beaglev] though.
+
+
+[visionfive]: https://github.com/starfive-tech/VisionFive
+[interest]: http://starfive.mikecrm.com/doQXj99
+[forum]: https://forum.rvspace.org/c/visionfive/6
+[starlight]: https://github.com/beagleboard/beaglev-starlight
+[soc]: https://github.com/starfive-tech/JH7100_Docs
+[beaglev]: https://beaglev.org/blog/2021-07-30-the-future-of-beaglev-community
+
+## Cross-compiling
+
+Cross-compiling the Linux kernel is surprisingly easy since it doesn't depend
+on any (target) libraries and most distributions already have packages with a
+working cross-compiler. We'll also need a few other tools to build everything:
+```shell
+# Debian/Ubuntu
+sudo apt-get install libncurses-dev libssl-dev bc flex bison make gcc gcc-riscv64-linux-gnu
+# Fedora
+sudo dnf install ncurses-devel openssl openssl-devel bc flex bison make gcc gcc-riscv64-linux-gnu
+# Archlinux
+sudo pacman -S --needed ncurses openssl bc flex bison make gcc riscv64-linux-gnu-gcc
+```
+
+The build system needs to know that we want to cross-compile a kernel for
+RISC-V by setting `ARCH=riscv`. It also needs to know the prefix of our
+cross-compiler using `CROSS_COMPILE=riscv64-linux-gnu-`. Also let's assume
+we're building on an 8-core machine so compilation can be greatly sped up by
+telling make to use all 8 cores with `-j8`.
+
+First we need to configure the kernel though. Linux has a *very* extensive
+configuration system, but you can get a good baseline configuration for the
+boards using:
+```shell
+make -j8 ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- visionfive_defconfig
+```
+
+There is nothing magic about this configuration other than it has all the
+drivers enabled that are working for the hardware on the boards. In fact it has
+very little extra features enabled which is great for compile times, but you
+are very much encouraged to add additional drivers and configure your kernel
+further using
+```shell
+make -j8 ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- nconfig
+```
+
+Now compile the whole thing with
+```
+make -j8 ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu-
+```
+
+
+## Installing
+
+Once the build has finished the resulting kernel can be found at
+```shell
+arch/riscv/boot/Image
+```
+You'll also need the matching device tree at
+```shell
+arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dtb
+```
+(If you have a Starlight board you should instead be using `jh7100-beaglev-starlight.dtb`.)
+
+These two files should be copied to the boot partition on the SD card. In the
+default [Fedora image][fedora] this is `/dev/mmcblk0p3` and is mounted at `/boot`.
+
+Now add the following entry to the `grub.cfg` file:
+```
+menuentry 'My New Kernel' {
+    linux /Image earlycon console=ttyS0,115200n8 root=/dev/mmcblk0p4 rootwait
+    devicetree /jh7100-starfive-visionfive-v1.dtb
+}
+```
+
+This assumes your root file system is at `/dev/mmcblk0p4` which it is in the
+default [Fedora image][fedora].
+
+The `visionfive_defconfig` doesn't enable modules, but if you enabled them in
+your build you'll also need to install them in `/lib/modules/` on the root file
+system. How to do that best is out of scope for this README though.
+
+[fedora]: https://github.com/starfive-tech/Fedora_on_StarFive/
+
+## Status
+
+#### SoC
+
+- [x] Clock tree
+- [x] Resets
+- [x] Pinctrl/Pinmux
+- [x] GPIO
+- [x] Serial port
+- [x] I2C
+- [x] SPI
+- [x] MMC / SDIO / SD card
+- [x] Random number generator
+- [x] Temperature sensor
+- [x] Ethernet
+- [x] USB, USB 3.0 is broken with `CONFIG_PM=y`
+- [x] DRM driver
+- [x] NVDLA
+- [x] Watchdog
+- [x] PWM DAC for sound through the minijack, only 16kHz samplerate for now
+- [ ] I2S [WIP]
+- [ ] TDM [WIP]
+- [ ] MIPI-DSI [WIP]
+- [ ] MIPI-CSI [WIP]
+- [ ] ISP [WIP]
+- [ ] Video Decode [WIP]
+- [ ] Video Encode [WIP]
+- [ ] QSPI
+- [ ] Security Engine
+- [ ] NNE50
+- [ ] Vision DSP
+
+#### Board
+
+- [x] LED
+- [x] PMIC / Reboot
+- [x] Ethernet PHY
+- [x] HDMI
+- [x] AP6236 Wifi
+- [x] AP6236 Bluetooth, with a [userspace tool][patchram]
+- [x] I2C EEPROM (VisionFive only)
+- [ ] GD25LQ128DWIG (VisionFive) / GD25LQ256D (Starlight) flash
+
+[patchram]: https://github.com/AsteroidOS/brcm-patchram-plus
+
+## Contributing
+
+If you're working on cleaning up or upstreaming some of this or adding support
+for more of the SoC I'd very much like to incorporate it into this tree. Either
+send a pull request, mail or contact Esmil on IRC/Slack.
+
+Also think of this tree mostly as a collection of patches that will hopefully
+mature enough to be submitted upstream eventually. So expect regular rebases.