MCP4725 DAC

Contents of Readme

1. About
2. Modules
3. Interface Description
4. Simulation
5. Test
6. Status Information
7. Issues
8. Licence

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About

MCP4725 is a 12-Bit Single Output DAC with EEPROM and I²C interface.

Modules

Module mcp4725 provides a simple interface for the MCP4725 DAC. Ports data_reg and mode_reg show current values of interface registers. These registers used to automatically update output values when input values changed. When enable held, high output value is kept at data_i and mode set to mode_i. When writeToMem is set, data_i and mode_i values are written to onboard EEPROM memory of the MCP4725 and internal registers data_reg and mode_reg are updated. When readFromMem is set, data_reg and mode_reg values are loaded from onboard EEPROM memory of the MCP4725.

Interface Description

Port	Type	Width	Description
clk	I	1	System Clock
rst	I	1	System Reset
SCL*	IO	1	I²C serial Clock
SDA*	IO	1	I²C data line
data_i	I	12	DAC voltage value input
data_reg	O	12	Current DAC voltage value
enable	I	1	Update output value
mode_i	I	2	Mode value input
mode_reg	O	2	Current mode value
writeToMem	I	1	Store given values to the memory
readFromMem	I	1	Load data from memory to data_reg and mode_reg
i2cSpeed	I	2	Select the frequency of SCL
A0	I	1	Address bit
clk_2x100kHz	I	1	200kHz Clock
clk_2x400kHz	I	1	800kHz Clock
clk_2x1_7MHz	I	1	3,4MHz Clock
clk_2x3_4MHz	I	1	6,8MHz Clock

I: Input O: Output

* Contains pins _i, _o and _t.

Note: Unused clock ports (clk_2x100kHz, clk_2x400kHz, clk_2x1_7MHz, clk_2x3_4MHz) can be left unconnected.

i2cSpeed value	Used clock
2'b00	clk_2x100kHz
2'b01	clk_2x400kHz
2'b10	clk_2x1_7MHz
2'b11	clk_2x3_4MHz

Note: Memory operations use clk_2x100kHz.

Simulation

Module mcp4725 simulated with sim.v. For simulation single write transaction is initiated. SDA is connected to pulldown to simulate slave acknowledgements.

Test

Module mcp4725 is tested with testboard.v on Digilent Basys 3. Twelve rightmost switches are connected to data_i. SW12 is used to control LSB of mode_i, MSB is set to 0. SW13 is connected to enable and two leftmost switches connected to i2cSpeed. Clock signals clk_2x100kHz, clk_2x400kHz, clk_2x1_7MHz and clk_2x3_4MHz generated by test clock generators included in mcp4725.v. Register data_reg is connected to seven segment display and twelve rightmost LEDs. Upper button is used to read from the memory and left button is used to write to the memory. SDA connected to JC4 and SCL connected to JC3. A0 value is set 0 and connected to A0 and JC2. Both I²C signals and analog output value is monitored.

For testing Adafruit MCP4725 Breakout Board is used. Normal modes (100kHz and 400kHz) are working, however high speed modes are not (1,7MHz and 3,4MHz).

Status Information

Last simulation: 25 January 2021, with Vivado Simulator.

Last test: 25 January 2021, on Digilent Basys 3.

Issues

• High speed mode implementation is not correct, will be corrected later.

License

CERN Open Hardware Licence Version 2 - Weakly Reciprocal