tiny risc-v (rv32i) implementation written in NSL

Requirements to build & test

• NSL
• iverilog
• gtkwave
• verilator

TODO

• fix dummy_memory for riscv-test
• riscv-formal
• ふぃぼなっち
  • libc もどき (_start and etc...)
• for FPGA
  • AXI-slave-LED
  • AXI-master
  • bootrom
    https://timetoexplore.net/blog/initialize-memory-in-verilog
  • UART
  • Linux
• rv6 on tiny_rv
• web interface

MEMO

$ cd core
$ make hex.nh TARGET=test_system MEMORY_HEX=../rv32ui-p-and.hex