Revise comment of MIE.MEIE #20
Merged
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Issue
The current comment incorrectly suggested that CLINT timer is controlled by MIE.MEIE.
Refer to RISC-V Privileged Spec, section 3.1 "Machine-Level CSRs v1.13" (p.43), the CLINT timer interrupt is controlled by
MIE.MTIE
(bit 7), whileMIE.MEIE
(bit 11) is for external interrupts.Fix
Updated the comment to clarify that
MIE.MEIE
enables external interrupts (e.g., UART).