Labwork on Logic Design implementation in Verilog on a Basys3 FPGA Module
-
Updated
Apr 13, 2024 - Tcl
Labwork on Logic Design implementation in Verilog on a Basys3 FPGA Module
This project provides an insight into the internal verification of a 32-bit single cycle processor that implements the Reduced Instruction Set-V and displayed on seven segment on Basys3 FPGA board. The hardware structures were realized using Verilog Hardware Description Language.
Add a description, image, and links to the 7-segment-display topic page so that developers can more easily learn about it.
To associate your repository with the 7-segment-display topic, visit your repo's landing page and select "manage topics."