Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA
-
Updated
Aug 3, 2022 - SystemVerilog
Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA
UART Receiver and Transmitter using Terasic DE-10 Standard FPGA
Basic Stopwatch Design using Terasic DE-10 Standard FPGA
DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
This repo is the lab materials for NTUEE DCLAB (http://dclab.ee.ntu.edu.tw).
Graph Processing Framework that supports || OpenMP || CAPI
Add a description, image, and links to the altera-fpga topic page so that developers can more easily learn about it.
To associate your repository with the altera-fpga topic, visit your repo's landing page and select "manage topics."