Repository gathering basic modules for CDC purpose
-
Updated
Dec 31, 2019 - SystemVerilog
Repository gathering basic modules for CDC purpose
A collection of debugging busses developed and presented at zipcpu.com
Audio Signal Processing SoC Project Website
Graph Processing Framework that supports || OpenMP || CAPI
Minimal SoC design for alarm clock
It contains 10 assignments based on simulation and testing of hardware codes on BASYS board.
Covers the DEEDS training material for electronic Design
Tetris in low level programming. Made for Nios II processors.
Add a description, image, and links to the fgpa topic page so that developers can more easily learn about it.
To associate your repository with the fgpa topic, visit your repo's landing page and select "manage topics."