Syntacore scr1 iALU verification example
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Updated
Mar 7, 2024 - SystemVerilog
Syntacore scr1 iALU verification example
32 bits CLA(Carry Lookahead Adder) and ALU RTL and verification. 32位块间超前的超前进位加法器及ALU设计与验证
10-bit MDR (Multiplication, division and square root calculator) implemented for the FPGA DE2-115 and for a ModelSim simulation. Coded in System Verilog ⚙️
An ALU implementation in System Verilog. Course project: Code upon request.
SystemVerlilog-Projects
UVM Test bench for a 8-bit ALU
A simple arithmetic logic unit (ALU) with System verilog
This is a modified version of the 32-bit MIPS microprocessor. Please refer to "manual.pdf" for more information.
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