#

bram

Here is 1 public repository matching this topic...

dpretet / meduram

Multi-port BRAM IP for ASIC and FPGA

block asic fpga ram yosys iverilog fusesoc bram amba axi4 axi4-lite multi-port svut axi4-lite-interface

Updated Apr 21, 2021
SystemVerilog

Improve this page

Add a description, image, and links to the bram topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the bram topic, visit your repo's landing page and select "manage topics."