a high performance library for building cache simulators
-
Updated
Apr 17, 2024 - C
a high performance library for building cache simulators
This C project is a cache simulation of a CPU containing L1D, L1I and L2 caches. It takes an image of memory and a memory trace as input, simulates the hit/miss behavior of a cache memory on this trace, and outputs the total number of hits, misses and evictions for each cache type along with the content of each cache at the end.
CPU Cache Simulation using gem5
Add a description, image, and links to the cache-simulation topic page so that developers can more easily learn about it.
To associate your repository with the cache-simulation topic, visit your repo's landing page and select "manage topics."