Memory hierarchy simulation, memory controller

A reference implementation for time-homogeneous Markov chain based cache

Cache Simulator for Computer Architecture course

🏜 Implementation of single-level cache simulator and analyze the performance of various cache architectures using real-world program traces.

Cache Remapping

The main purpose of this project is to understand MIPS Assembly language. The input of this program is a file consisting sequence of MIPS instructions in binary. This version expands the first to implement behaviour of cache. At the end of the execution, the simulator reports the number of total cache hits and misses. These programs contain 500+…

MESI Cache Coherency Protocol Simulator - Trabalho para a Disciplina de Arquitetura e Organização de Computadores II

Simulate a fully-associative LRU cache with user-modifiable block number

A cache simulator used to test out the performance of different cache configurations by analyzing hit and miss patterns on real cache trace data.

Code which simulates the working of a cache memory

Repo for all computer architecture stuff this year

A very basic L2-L3 cache hierarchy trace based simulator. The cache implements LRU as the page replacement policy.

Tracing and various analysis of Multi Threaded Programs.

Cache simulator backend.