4 bit divider design using first divider algorithm
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Updated
Aug 17, 2021 - Verilog
4 bit divider design using first divider algorithm
This repository contains a few useful Verilog modules
PWM module using verilig HDL in XILINX ISE
RTL Designs along with testbenches to verify them written in Verilog. Icarus Verilog an open source simulator was used for simulations.
Full AES (Verilog)
This repository contains scripts that I create through my digital design course in Verilog, VHDL, SystemVerilog etc..
5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
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