This repository contains scripts that I create through my digital design course in Verilog, VHDL, SystemVerilog etc..
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Updated
Mar 16, 2020 - Verilog
This repository contains scripts that I create through my digital design course in Verilog, VHDL, SystemVerilog etc..
This repository contains a few useful Verilog modules
PWM module using verilig HDL in XILINX ISE
4 bit divider design using first divider algorithm
5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
RTL Designs along with testbenches to verify them written in Verilog. Icarus Verilog an open source simulator was used for simulations.
Full AES (Verilog)
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